ZHCSGM6C February   2017  – April 2020 DAC38RF82 , DAC38RF89

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     32x6MHz 256QAM 载波
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - DC Specifications
    6. 7.6  Electrical Characteristics - Digital Specifications
    7. 7.7  Electrical Characteristics - AC Specifications
    8. 7.8  PLL/VCO Electrical Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  SerDes Inputs
      2. 8.3.2  SerDes Rate
      3. 8.3.3  SerDes PLL
      4. 8.3.4  SerDes Equalizer
      5. 8.3.5  JESD204B Descrambler
      6. 8.3.6  JESD204B Frame Assembly
      7. 8.3.7  SYNC Interface
      8. 8.3.8  Single or Dual Link Configuration
      9. 8.3.9  Multi-Device Synchronization
      10. 8.3.10 SYSREF Capture Circuit
      11. 8.3.11 JESD204B Subclass 0 Support
      12. 8.3.12 SerDes Test Modes through Serial Programming
      13. 8.3.13 SerDes Test Modes through IEEE 1500 Programming
      14. 8.3.14 Error Counter
      15. 8.3.15 Eye Scan
      16. 8.3.16 JESD204B Pattern Test
      17. 8.3.17 Wideband DUC (wide-DUC)
      18. 8.3.18 Interpolation Block
        1. 8.3.18.1 Multi-DUC input
        2. 8.3.18.2 Interpolation Filters
        3. 8.3.18.3 JESD204B Modes, Interpolation and Clock phase Programming
        4. 8.3.18.4 Digital Quadrature Modulator
        5. 8.3.18.5 Low Power Coarse Resolution Mixing Modes
        6. 8.3.18.6 Inverse Sinc Filter
      19. 8.3.19 PA Protection Block
      20. 8.3.20 Gain Block
      21. 8.3.21 Output Summation
      22. 8.3.22 Output Delay
      23. 8.3.23 Polarity Inversion
      24. 8.3.24 Temperature Sensor
      25. 8.3.25 Alarm Monitoring
      26. 8.3.26 Differential Clock Inputs
      27. 8.3.27 CMOS Digital Inputs
      28. 8.3.28 DAC Fullscale Output Current
      29. 8.3.29 Current Steering DAC Architecture
      30. 8.3.30 DAC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clocking Modes
      2. 8.4.2 PLL Bypass Mode Programming
      3. 8.4.3 Internal PLL/VCO
      4. 8.4.4 CLKOUT
      5. 8.4.5 Serial Peripheral Interface (SPI)
        1. 8.4.5.1 NORMAL (RW)
        2. 8.4.5.2 WRITE_TO_CLEAR (W0C)
    5. 8.5 Register Maps
      1. 8.5.1  Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
        1. Table 48. RESET_CONFIG Field Descriptions
      2. 8.5.2  IO Configuration Register (address = 0x01) [reset = 0x1800]
        1. Table 49. IO_CONFIG Field Descriptions
      3. 8.5.3  Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
        1. Table 50. ALM_SD_MASK Field Descriptions
      4. 8.5.4  Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
        1. Table 51. ALM_CLK_MASK Field Descriptions
      5. 8.5.5  SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = 0x0000]
        1. Table 52. ALM_SD_DET Field Descriptions
      6. 8.5.6  SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = 0x0000]
        1. Table 53. ALM_SYSREF_DET Field Descriptions
      7. 8.5.7  Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
        1. Table 54. TEMP_PLLVOLT Field Descriptions
      8. 8.5.8  Page Set Register (address = 0x09) [reset = 0x0000]
        1. Table 55. PAGE_SET Field Descriptions
      9. 8.5.9  SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
        1. Table 56. SYSREF_ALIGN_R Field Descriptions
      10. 8.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
        1. Table 57. SYSREF12_CNT Field Descriptions
      11. 8.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
        1. Table 58. SYSREF34_CNT Field Descriptions
      12. 8.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0008]]
        1. Table 59. VENDOR_VER Field Descriptions
      13. 8.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
        1. Table 60. MULTIDUC_CFG1 Field Descriptions
      14. 8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
        1. Table 61. MULTIDUC_CFG2 Field Descriptions
      15. 8.5.15 JESD FIFO Control Register (address = 0x0D) [reset = 0x1300]
        1. Table 62. JESD_FIFO Field Descriptions
      16. 8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
        1. Table 63. ALM_MASK1 Field Descriptions
      17. 8.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
        1. Table 64. ALM_MASK2 Field Descriptions
      18. 8.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
        1. Table 65. ALM_MASK3 Field Descriptions
      19. 8.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
        1. Table 66. ALM_MASK4 Field Descriptions
      20. 8.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
        1. Table 67. JESD_LN_SKEW Field Descriptions
      21. 8.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
        1. Table 68. CMIX Field Descriptions
      22. 8.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
        1. Table 69. OUTSUM Field Descriptions
      23. 8.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
        1. Table 70. PHASE_NCOAB Field Descriptions
      24. 8.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
        1. Table 71. PHASE_NCOCD Field Descriptions
      25. 8.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
        1. Table 72. FREQ_NCOAB Field Descriptions
      26. 8.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
        1. Table 73. FREQ_NCOCD Field Descriptions
      27. 8.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
        1. Table 74. SYSREF_CLKDIV Field Descriptions
      28. 8.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
        1. Table 75. SERDES_CLK Field Descriptions
      29. 8.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
        1. Table 76. SYNCSEL1 Field Descriptions
      30. 8.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
        1. Table 77. SYNCSEL2 Field Descriptions
      31. 8.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
        1. Table 78. PAP_GAIN_AB Field Descriptions
      32. 8.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
        1. Table 79. PAP_WAIT_AB Field Descriptions
      33. 8.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
        1. Table 80. PAP_GAIN_CD Field Descriptions
      34. 8.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
        1. Table 81. PAP_WAIT_CD Field Descriptions
      35. 8.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
        1. Table 82. PAP_CFG_AB Field Descriptions
      36. 8.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
        1. Table 83. PAP_CFG_CD Field Descriptions
      37. 8.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
        1. Table 84. SPIDAC_TEST1 Field Descriptions
      38. 8.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
        1. Table 85. SPIDAC_TEST2 Field Descriptions
      39. 8.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0000]
        1. Table 86. GAINAB Field Descriptions
      40. 8.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0000]
        1. Table 87. GAINCD Field Descriptions
      41. 8.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
        1. Table 88. JESD_ERR_CNT Field Descriptions
      42. 8.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
        1. Table 89. JESD_ID1 Field Descriptions
      43. 8.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
        1. Table 90. JESD ID 2 Register (JESD_ID2)
      44. 8.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
        1. Table 91. JESD_ID3 Field Descriptions
      45. 8.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
        1. Table 92. JESD_LN_EN Field Descriptions
      46. 8.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
        1. Table 93. JESD_RBD_F Field Descriptions
      47. 8.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
        1. Table 94. JESD_K_L Field Descriptions
      48. 8.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
        1. Table 95. JESD_M_S Field Descriptions
      49. 8.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
        1. Table 96. JESD_N_HD_SCR Field Descriptions
      50. 8.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
        1. Table 97. JESD_MATCH Field Descriptions
      51. 8.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
        1. Table 98. JESD_Link_CFG Field Descriptions
      52. 8.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
        1. Table 99. JESD_SYNC_REQ Field Descriptions
      53. 8.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
        1. Table 100. JESD_ERR_OUT Field Descriptions
      54. 8.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
        1. Table 101. JESD_ILA_CFG1 Field Descriptions
      55. 8.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
        1. Table 102. JESD_ILA_CFG2 Field Descriptions
      56. 8.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
        1. Table 103. JESD_SYSR_MODE Field Descriptions
      57. 8.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
        1. Table 104. JESD_CROSSBAR1 Field Descriptions
      58. 8.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
        1. Table 105. JESD_CROSSBAR2 Field Descriptions
      59. 8.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
        1. Table 106. JESD_ALM_L0 Field Descriptions
      60. 8.5.60 JESD Alarms for Lane 1 Register (address = 0x65 01100101) [reset = 0x0000]
        1. Table 107. JESD_ALM_L1 Field Descriptions
      61. 8.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
        1. Table 108. JESD_ALM_L2 Field Descriptions
      62. 8.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
        1. Table 109. JESD_ALM_L3 Field Descriptions
      63. 8.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
        1. Table 110. JESD_ALM_L4 Field Descriptions
      64. 8.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
        1. Table 111. JESD_ALM_L5 Field Descriptions
      65. 8.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
        1. Table 112. JESD_ALM_L6 Field Descriptions
      66. 8.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
        1. Table 113. JESD Alarms for Lane 7 Register (JESD_ALM_L7)
      67. 8.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
        1. Table 114. ALM_SYSREF_PAP Field Descriptions
      68. 8.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
        1. Table 115. ALM_CLKDIV1 Field Descriptions
      69. 8.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xF000]
        1. Table 116. CLK_CONFIG Field Descriptions
      70. 8.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
        1. Table 117. SLEEP_CONFIG Field Descriptions
      71. 8.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x8000]
        1. Table 118. CLK_OUT Field Descriptions
      72. 8.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
        1. Table 119. DACFS Field Descriptions
      73. 8.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
        1. Table 120. LCMGEN Field Descriptions
      74. 8.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
        1. Table 121. LCMGEN_DIV Field Descriptions
      75. 8.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
        1. Table 122. LCMGEN_SPISYSREF Field Descriptions
      76. 8.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
        1. Table 123. DTEST Field Descriptions
      77. 8.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
        1. Table 124. SLEEP_CNTL Field Descriptions
      78. 8.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
        1. Table 125. SYSR_CAPTURE Field Descriptions
      79. 8.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
        1. Table 126. Clock Input and PLL Configuration Register (CLK_PLL_CFG)
      80. 8.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
        1. Table 127. CONFIG1 Field Descriptions
      81. 8.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
        1. Table 128. PLL_CONFIG2 Field Descriptions
      82. 8.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
        1. Table 129. LVDS_CONFIG Field Descriptions
      83. 8.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
        1. Table 130. PLL_FDIV Field Descriptions
      84. 8.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x0002]
        1. Table 131. SRDS_CLK_CFG Field Descriptions
      85. 8.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
        1. Table 132. SRDS_PLL_CFG Field Descriptions
      86. 8.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
        1. Table 133. RDS_CFG1 Field Descriptions
      87. 8.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
        1. Table 134. SRDS_CFG2 Field Descriptions
      88. 8.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
        1. Table 135. SRDS_POL Field Descriptions
      89. 8.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
        1. Table 136. SYNCBOUT Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-up Sequence
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Calculating the JESD204B SerDes rate
      4. 9.2.4 Calculating valid JESD204B SYSREF Frequency
      5. 9.2.5 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.5 Register Maps

Table 47. Register Summary

Address Reset Acronym Register Name Section
General Configuration Registers (PAGE_SET[2:0] = 000)
0x00 0x5803 RESET_CONFIG Chip Reset and Configuration 8.5.1
0x01 0x1800 IO_CONFIG IO Configuration 8.5.2
0x02 0xFFFF ALM_SD_MASK Lane Signal Detect Alarm Mask 8.5.3
0x03 0xFFFF ALM_CLK_MASK Clock Alarms Mask 8.5.4
0x04 0x0000 ALM_SD_DET SERDES Loss of Signal Detection Alarms 8.5.5
0x05 0x0000 ALM_SYSREF_DET SYSREF Alignment Circuit Alarms 8.5.6
0x06 variable TEMP_PLLVOLT Temperature Sensor and PLL Loop Voltage 8.5.7
0x07-0x08 0x0000 Reserved Reserved
0x09 0x0000 PAGE_SET Page Set 8.5.8
0x0A-0x77 0x0000 Reserved Reserved
0x78 0x0000 SYSREF_ALIGN_R SYSERF Align to r1 and r3 Count 8.5.9
0x79 0x0000 SYSREF12_CNT SYSREF Phase Count 1 and 2 8.5.10
0x7A 0x0000 SYSREF34_CNT SYSREF Phase Count 3 and 4 8.5.11
0x7B-0x7E 0x0000 Reserved Reserved
0x7F 0x0008 VENDOR_VER Vendor ID and Chip Version 8.5.12
Multi-DUC Configuration Registers (PAGE_SET[0] = 1 for multi-DUC1, PAGE_SET[1] = 1 for multi-DUC2)
0x0A 0x02B0 MULTIDUC_CFG1 Multi-DUC Configuration (PAP, Interpolation) 8.5.13
0x0B 0x0000 Reserved Reserved
0x0C 0x2402 MULTIDUC_CFG2 Multi-DUC Configuration (Mixers) 8.5.14
0x0D 0x8300 JESD_FIFO JESD FIFO Control 8.5.15
0x0E 0x00FF ALM_MASK1 Alarm Mask 1 8.5.16
0x0F 0x1F83 ALM_MASK2 Alarm Mask 2 8.5.17
0x10 0xFFFF ALM_MASK3 Alarm Mask 3 8.5.18
0x11 0xFFFF ALM_MASK4 Alarm Mask 4 8.5.19
0x12 0x0000 JESD_LN_SKEW JESD Lane Skew 8.5.20
0x13-0x16 0x0000 Reserved Reserved
0x17 0x0000 CMIX CMIX Configuration 8.5.21
0x18 0x0000 Reserved Reserved
0x19 0x0000 OUTSUM Output Summation and Delay 8.5.22
0x1A-0x1B 0x0000 Reserved Reserved
0x1C 0x0000 PHASE_NCOAB Phase offset for AB path NCO 8.5.23
0x1D 0x0000 PHASE_NCOCD Phase offset for CD path NCO 8.5.24
0x1E-0x20 0x0000 FREQ_NCOAB Frequency for AB path NCO 8.5.25
0x21-0x23 0x0000 FREQ_NCOCD Frequency for CD path NCO 8.5.26
0x24 0x0010 SYSREF_CLKDIV SYSREF Use for Clock Divider 8.5.27
0x25 0x7700 SERDES_CLK Serdes Clock Control 8.5.28
0x26 0x0000 Reserved Reserved
0x27 0x1144 SYNCSEL1 Sync Source Selection 8.5.29
0x28 0x0000 SYNCSEL2 Sync Source Selection 8.5.30
0x29 0x0000 PAP_GAIN_AB PAP path AB Gain Attenuation Step 8.5.31
0x2A 0x0000 PAP_WAIT_AB PAP path AB Wait Time at Gain = 0 8.5.32
0x2B 0x0000 PAP_GAIN_CD PAP path CD Gain Attenuation Step 8.5.33
0x2C 0x0000 PAP_WAIT_CD PAP path CD Wait Time at Gain = 0 8.5.34
0x2D 0x1FFF PAP_CFG_AB PAP path AB Configuration 8.5.35
0x2E 0x1FFF PAP_CFG_CD PAP path CD Configuration 8.5.36
0x2F 0x0000 SPIDAC_TEST1 Configuration for DAC SPI Constant 8.5.37
0x30 0x0000 SPIDAC_TEST2 DAC SPI Constant 8.5.38
0x31 0x0000 Reserved Reserved
0x32 0x0800 GAINAB Gain for path AB 8.5.39
0x33 0x0800 GAINCD Gain for path CD 8.5.40
0x34-0x40 0x0000 Reserved Reserved
0x41 0x0000 JESD_ERR_CNT JESD Error Counter 8.5.41
0x42-0x45 0x0000 Reserved Reserved
0x46 0x0044 JESD_ID1 JESD ID 1 8.5.42
0x47 0x190A JESD_ID2 JESD ID 2 8.5.43
0x48 0x31C3 JESD_ID3 JESD ID 3 and Subclass 8.5.44
0x49 0x0000 Reserved Reserved
0x4A 0x0003 JESD_LN_EN JESD Lane Enable 8.5.45
0x4B 0x1300 JESD_RBD_F JESD RBD Buffer and Frame Octets 8.5.46
0x4C 0x1303 JESD_K_L JESD K and L Parameters 8.5.47
0x4D 0x0100 JESD_M_S JESD M and S Parameters 8.5.48
0x4E 0x0F4F JESD_N_HD_SCR JESD N, HD and SCR Parameters 8.5.49
0x4F 0x1CC1 JESD_MATCH JESD Character Match and Other 8.5.50
0x50 0x0000 JESD_LINK_CFG JESD Link Configuration Data 8.5.51
0x51 0x00FF JESD_SYNC_REQ JESD Sync Request 8.5.52
0x52 0x00FF JESD_ERR_OUT JESD Error Output 8.5.53
0x53 0x0100 JESD_ILA_CFG1 JESD Configuration Value used for ILA Check 8.5.54
0x54 0x8E60 JESD_ILA_CFG2 JESD Configuration Value used for ILA Check 8.5.55
0x55-0x5B 0x0000 Reserved Reserved
0x5C 0x0001 JESD_SYSR_MODE JESD SYSREF Mode 8.5.56
0x5D-0x5E 0x0000 Reserved Reserved
0x5F 0x0123 JESD_CROSSBAR1 JESD Crossbar Configuration 1 8.5.57
0x60 0x4567 JESD_CROSSBAR2 JESD Crossbar Configuration 2 8.5.58
0x61-0x63 0x0000 Reserved Reserved
0x64 0x0000 JESD_ALM_L0 JESD Alarms for Lane 0 8.5.59
0x65 0x0000 JESD_ ALM_L1 JESD Alarms for Lane 1 8.5.60
0x66 0x0000 JESD_ ALM_L2 JESD Alarms for Lane 2 8.5.61
0x67 0x0000 JESD_ALM_L3 JESD Alarms for Lane 3 8.5.62
0x68 0x0000 JESD_ALM_L4 JESD Alarms for Lane 4 8.5.63
0x69 0x0000 JESD_ALM_L5 JESD Alarms for Lane 5 8.5.64
0x6A 0x0000 JESD_ALM_L6 JESD Alarms for Lane 6 8.5.65
0x6B 0x0000 JESD_ALM_L7 JESD Alarms for Lane 7 8.5.66
0x6C 0x0000 ALM_SYSREF_PAP SYSREF and PAP Alarms 8.5.67
0x6D 0x0000 ALM_CLKDIV1 Clock Divider Alarms 1 8.5.68
0x6E-0x77 0x0000 Reserved Reserved
Miscellaneous Configuration Registers (PAGE_SET[1:0] = 00, PAGE_SET[2] = 1)
0x0A 0xFC03 CLK_CONFIG Clock Configuration 8.5.69
0x0B 0x0022 SLEEP_CONFIG Sleep Configuration 8.5.70
0x0C 0xA002 CLK_OUT Divided Output Clock Configuration 8.5.71
0x0D 0xF000 DACFS DAC Fullscale Current 8.5.72
0x0E-0x0F 0x0000 Reserved Reserved
0x10 0x0000 LCMGEN Internal sysref generator 8.5.73
0x11 0x0000 LCMGEN_DIV Counter for internal sysref generator 8.5.74
0x12 0x0000 LCMGEN_SPISYSREF SPI SYSREF for internal sysref generator 8.5.75
0x13-0x1A 0x0000 Reserved Reserved
0x1B 0x0000 DTEST Digital Test Signals 8.5.76
0x1C-0x22 0x0000 Reserved Reserved
0x23 0x03F3 SLEEP_CNTL Sleep Pin Control 8.5.77
0x24 0x1000 SYSR_CAPTURE SYSREF Capture Circuit Control 8.5.78
0x25-0x30 0x0000 Reserved Reserved
0x31 0x0200 CLK_PLL_CFG Clock Input and PLL Configuration 8.5.79
0x32 0x0308 PLL_CONFIG1 PLL Configuration 1 8.5.80
0x33 0x4018 PLL_CONFIG2 PLL Configuration 2 8.5.81
0x34 0x0000 LVDS_CONFIG LVDS Output Configuration 8.5.82
0x35 0x0018 PLL_FDIV Fuse farm clock divider 8.5.83
0x36-0x3A 0x0000 Reserved Reserved
0x3B 0x0002 SRDS_CLK_CFG Serdes Clock Configuration 8.5.84
0x3C 0x8228 SRDS_PLL_CFG Serdes PLL Configuration 8.5.85
0x3D 0x0088 SRDS_CFG1 Serdes Configuration 1 8.5.86
0x3E 0x0909 SRDS_CFG2 Serdes Configuration 2 8.5.87
0x3F 0x0000 SRDS_POL Serdes Polarity Control 8.5.88
0x40-0x75 0x0000 Reserved Reserved
0x76 0x0000 SYNCBOUT JESD204B SYNCB Output 8.5.89