ZHCSGV7F July   2017  – January 2024 CDCI6214

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  EEPROM Characteristics
    6. 6.6  Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P, FB_N)
    7. 6.7  Reference Input, Crystal Mode Characteristics (XIN, XOUT)
    8. 6.8  General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)
    9. 6.9  Triple Level Input Characteristics (EEPROMSEL, REFSEL)
    10. 6.10 Reference Mux Characteristics
    11. 6.11 Phase-Locked Loop Characteristics
    12. 6.12 Closed-Loop Output Jitter Characteristics
    13. 6.13 Output Mux Characteristics
    14. 6.14 LVCMOS Output Characteristics
    15. 6.15 HCSL Output Characteristics
    16. 6.16 LVDS DC-Coupled Output Characteristics
    17. 6.17 Programmable Differential AC-Coupled Output Characteristics
    18. 6.18 Output Skew and Delay Characteristics
    19. 6.19 Output Synchronization Characteristics
    20. 6.20 Timing Characteristics
    21. 6.21 I2C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)
    22. 6.22 Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)
    23. 6.23 Power Supply Characteristics
    24. 6.24 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Parameters
      1. 7.1.1 Reference Inputs
      2. 7.1.2 Outputs
      3. 7.1.3 Serial Interface
      4. 7.1.4 Power Supply
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference Block
        1. 8.3.1.1 Input Stages
          1. 8.3.1.1.1 Crystal Oscillator
          2. 8.3.1.1.2 LVCMOS
          3. 8.3.1.1.3 Differential AC-Coupled
        2. 8.3.1.2 Reference Mux
        3. 8.3.1.3 Reference Divider
          1. 8.3.1.3.1 Doubler
        4. 8.3.1.4 Bypass-Mux
        5. 8.3.1.5 Zero Delay, Internal and External Path
      2. 8.3.2 Phase-Locked Loop
      3. 8.3.3 Clock Distribution
        1. 8.3.3.1 Output Channel
        2. 8.3.3.2 Divider Glitch-Less Update
      4. 8.3.4 Control Pins
        1. 8.3.4.1 Global and Individual Output Enable: OE and OE_Y[4:1]
      5. 8.3.5 Operation Modes
      6. 8.3.6 Divider Synchronization - SYNC
      7. 8.3.7 EEPROM - Cyclic Redundancy Check
      8. 8.3.8 Power Supplies
        1. 8.3.8.1 Power Management
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Mode
      2. 8.4.2 Serial Interface Mode
        1. 8.4.2.1 Fall-Back Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Procedure
      2. 8.5.2 EEPROM Access
      3. 8.5.3 Device Defaults
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Power-Up Sequence
      2. 9.5.2 De-Coupling
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Examples
  11. 10Register Maps
    1. 10.1 CDCI6214 Registers
    2. 10.2 EEPROM Map
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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8.3.4 Control Pins

The ultra-low power clock generator is controlled by multiple LVCMOS input pins.

EEPROMSEL acts as EEPROM page select. The CDCI6214 clock generator contains two pages of configuration settings. The level of this pin is sampled after device power-up. A low level selects page zero. A high level selects page one. The EEPROMSEL pin is a tri-level input pin. This third voltage level is automatically applied by an internal voltage divider. The mid-level is used to select an internal default where the serial interface is enabled.

RESETN/SYNC (pin 8) , SCL (pin 12), and SDA (pin 19) have a secondary functionality and can act as general-purpose inputs and outputs (GPIO). This means that either the serial interface or the GPIO functionality can be active.

RESETN/SYNC resets the internal circuitry and is used in the initial power-up sequence. The pin can be reconfigured to act as synchronization input. The differential outputs are kept in mute while SYNC is low. When SYNC is high, outputs are active. Moreover status signals can be driven by this pin.

SCL can act as general-purpose input.

SDA can act as general-purpose input and output.

REFSEL is used to select between the input references to the PLL. A low level selects the crystal reference on XIN. A high level selects the differential input reference on REFP, REFN.

Table 8-6 Control and GPIO List
PINRECONFIGURABLE?INPUTOUTPUTTERMINATION
NO.NAMEGPIO2-LOGIC-LEVELS3-LOGIC-LEVELS2-LEVELPULLDOWNPULLUP
23EEPROMSEL-––yes–50 kΩ50 kΩ
20STATUSGPIO1yesyes–yes–50 kΩ
19SDAGPIO2yesyes–yes––
12SCLGPIO3yesyes––––
11OEGPIO4yesyes–yes–50 kΩ
8RESETNGPIO0yesyes–yes–50 kΩ
4REFSEL-––yes–50 kΩ50 kΩ
Table 8-7 GPIO - Input Signal List
SIGNAL NO. (1)ABBREVIATIONDESCRIPTION
0FREQ_INCFrequency increment; increments the IOD(2)
1FREQ_DECFrequency decrement; decrements the IOD.(2)
2OE (global)Enables or disables all differential outputs Y[4:1] (bypass not affected).(3)
4OE_Y1Enables or disables Y1. (3)
5OE_Y2Enables or disables Y2. (3)
6OE_Y3Enables or disables Y3. (3)
7OE_Y4Enables or disables Y4. (3)
(1) Signals from this list are available on pin 11 (OE / GPIO4) and pin 20 (STATUS / GPIO1), see

GENERIC1.

(2) Selected using bit mask in GENERIC3.
(3) Disable / Mute behaviour configured individually using ch_mute_sel bit in GENERIC0 table.
Table 8-8 GPIO - Output Signal List
SIGNAL NO.(1) ABBREVIATIONDESCRIPTION
0PLL_LOCK0 = PLL out of lock; 1 = indicates PLL in lock
1XTAL_OSC0 = crystal failure; 1 = crystal oscillates
2CAL_DONE0 = PLL (VCO) calibration ongoing; 1 = calibration done
3CONF_DONE0 = device logic busy; 1 = device operational
4SYNC_DONE0 = output sync ongoing, muted; 1 = outputs released operational
5EEPROM_BUSY0 = EEPROM idle; 1 = EEPROM access ongoing
6EEPROM_Y120 = EEPROM pin sees low level; 1 = EEPROM pin sees high level
7EEPROM_M120 = EEPROM pin sees low or high level; 1 = EEPROM pin sees mid level
8I2C_LSBIndicates I2C target address LSB config from loaded EEPROM
9CLK_FSMClock, State machine
10CLK_PFD_REFClock, PFD, reference
11CLK_PFD_FBClock, PFD, feedback
12BUF_SYNCbuffered SYNC pin
13BUF_SCLbuffered SCL pin
14BUF_SDAbuffered received SDA pin
(1) Signals from this list are available on pin 8 (RESETN/SYNC or GPIO0), pin 11 (OE / GPIO4) and pin 20 (STATUS / GPIO1).