ZHCSIP0G November 2009 – November 2022 CDC3RL02
PRODUCTION DATA
The designer must make sure that all parameters are within the ranges specified in Section 7.3.
Each device which receives a clock output from the CDC3RL02 should have the CLK request pin connected to the appropriate CLK_REQ pin on the CDC3RL02. This will enable the output buffer when a device requests the clock signal.
It is possible to have a control the outputs of the clock by using a GPIO from a controller to control the CLK_REQ pins.
If one of the outputs is unused, then tie the CLK_REQ and CLK_OUT pins to ground. If the user wants a CLK_OUT pin always enabled, it is acceptable to tie the paired CLK_REQ pin to an external 1.8-V source (not VLDO because the LDO output is not enabled until at least one CLK_REQ pin is high).