ZHCSIP0G November   2009  – November 2022 CDC3RL02

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low Additive Noise
      2. 8.3.2 Regulated 1.8-V Externally Available I/O Supply
      3. 8.3.3 Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP Package
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Clock Squarer
      2. 9.1.2 Output Stage
      3. 9.1.3 LDO
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
LDO
VOUTLDO output voltageIOUT = 50 mA1.711.81.89V
CLDOExternal load capacitance110μF
IOUT(SC)Short circuit output currentRL = 0 Ω100mA
IOUT(PK)Peak output currentVBATT = 2.3 V, VLDO = VOUT – 5%100mA
PSRPower supply rejectionVBATT = 2.3 V, IOUT = 2 mA,fIN= 217 Hz and 1 kHz60dB
fIN= 3.25 MHz40
tsuLDO startup timeVBATT = 2.3 V , CLDO = 1 μF,
CLK_REQ_n to VIH = 1.71 V		0.2ms
VBATT = 5.5 V , CLDO = 10 μF,
CLK_REQ_n to VIH = 1.71 V		1
POWER CONSUMPTION
ISBStandby currentDevice in standby (all VCLK_REQ_n = 0 V)0.21μA
ICCSStatic current consumptionDevice active but not switching0.41mA
IOBOutput buffer average currentfIN = 26 MHz, CLOAD = 50 pF4.2mA
CPDOutput power dissipation capacitancefIN = 26 MHz44pF
MCLK_IN INPUT
IIMCLK_IN, CLK_REQ_1/2 leakage currentVI = VIH or GND1μA
CIMCLK_IN capacitancefIN = 26 MHz4.75pF
RIMCLK_IN impedancefIN = 26 MHz6kΩ
fINMCLK_IN frequency range102680MHz
MCLK_IN LVCMOS SOURCE
Additive phase noisefIN = 26 MHz, tr/tf ≤ 1 ns1-kHz offset–140dBc/Hz
10-kHz offset–149
100-kHz offset–153
1-MHz offset–148
Additive jitterfIN = 26 MHz, VPP = 0.8 V, BW = 10–5 MHz0.37ps (rms)
tDLMCLK_IN to CLK_OUT_n propagation delay11ns
DCLOutput duty cyclefIN = 26 MHz, DCIN = 50%45%50%55%
MCLK_IN SINUSOIDAL SOURCE
VMAInput amplitude0.31.8V
Additive phase noisefIN = 26 MHz, VMA = 1.8 VPP1-kHz offset–141dBc/Hz
10-kHz offset–149
100-kHz offset–152
1-MHz offset–148
fIN = 26 MHz, VMA = 0.8 VPP1-kHz offset–139
10-kHz offset–146
100-kHz offset–150
1-MHz offset–146
Additive jitterfIN = 26 MHz, VMA = 1.8 VPP, BW = 10–5 MHz0.41ps (RMS)
tDSMCLK_IN to CLK_OUT_1/2 propagation delay12ns
DCsOutput duty cyclefIN = 26 MHz, VMA > 1.8 VPP45%50%55%
CLK_OUT_N OUTPUTS
tr20% to 80% rise timeCL = 10 pF to 50 pF15.2ns
tf20% to 80% fall timeCL = 10 pF to 50 pF15.2ns
tskChannel-to-channel skewCL = 10 pF to 50 pF (CL1 = CL2)–0.50.5ns
VOHHigh-level output voltageIOH = –100 μA, reference to VLDO–0.1V
IOH = –8 mA1.2
VOLLow-level output voltageIOL = 20 μA0.2V
IOL = 8 mA0.55