ZHCSHD3J October   2017  – December 2022 BQ2980 , BQ2982

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Configurability
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Overvoltage (OV) Status
      2. 8.3.2 Undervoltage (UV) Status
      3. 8.3.3 Overcurrent in Charge (OCC) Status
      4. 8.3.4 Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) Status
      5. 8.3.5 Overtemperature (OT) Status
      6. 8.3.6 Charge and Discharge Driver
      7. 8.3.7 CTR for FET Override and Device Shutdown
      8. 8.3.8 CTR for PTC Connection
      9. 8.3.9 ZVCHG (0-V Charging)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 Power-On-Reset (POR)
        2. 8.4.1.2 NORMAL Mode
        3. 8.4.1.3 FAULT Mode
        4. 8.4.1.4 SHUTDOWN Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Test Circuits for Device Evaluation
      2. 9.1.2 Test Circuit Diagrams
      3. 9.1.3 Using CTR as FET Driver On/Off Control
    2. 9.2 Typical Applications
      1. 9.2.1 BQ298x Configuration 1: System-Controlled Reset/Shutdown Function
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Selection of Power FET
        4. 9.2.1.4 Application Curves
      2. 9.2.2 BQ298x Configuration 2: CTR Function Disabled
      3. 9.2.3 BQ298x Configuration 3: PTC Thermistor Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.3.7 CTR for FET Override and Device Shutdown

The CTR pin is an active-high input pin, which can be controlled by the host system to turn off both CHG and DSG outputs momentarily to reset the system, shut down the system for low-power storage, or as a necessary shutdown if the host detects a critical system error.

The CTR pin uses a 4.5-s timer (same specification tolerance as the tOVP delay 4.5-s option) to differentiate a reset and shutdown signal. CHG and DSG are off when VCTR > CTR VIH for > 200 µs. Counting from the start of VCTR > VIH, if VCTR drops below VIL within 3.6 s, CHG and DSG simply turn back on. If CTR remains HIGH for > 5.4 s, the device enters SHUTDOWN mode.

With this timing control, the system designer can use an RC circuit to implement either a host-controlled power-on-reset or a system shutdown.

GUID-34105BD9-C496-4199-88FD-3BB06982A123-low.gifFigure 8-1 CTR Level in Rising and Falling Direction
Note:

  • CTR shuts down the device only when VCTR is HIGH for > 5.4 s AND when there is no OV or OT fault present.
  • The CTR VIH level is the voltage level at which the CTR pin is considered HIGH in the positive direction as voltage increases. There is a minimum hysteresis designed into the logic level; therefore, as voltage decreases, CTR is considered HIGH at the (VIH – VHYS) level.
  • The FET override and the shutdown functions are not available if the CTR pull-up is enabled. See Section 8.3.8 for details.

GUID-38A162EF-574B-4F9D-9DDB-FB2245DF2193-low.gifFigure 8-2 System Reset Function Implementation
GUID-6E6D2CFC-E247-4435-A9F9-B099AEF3764A-low.gifFigure 8-3 Potential System- Controlled Shutdown Implementation