ZHCSU23A October   2023  – December 2023 BQ25638

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 说明（续）
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On-Reset (POR)
      2. 7.3.2  Device Power Up from Battery
      3. 7.3.3  Device Power Up from Input Source
        1. 7.3.3.1 REGN LDO Power Up
        2. 7.3.3.2 Poor Source Qualification
        3. 7.3.3.3 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        4. 7.3.3.4 Converter Power-Up
        5. 7.3.3.5 Input Current Optimizer (ICO)
        6. 7.3.3.6 Switching Frequency and Dithering Feature
      4. 7.3.4  Power Path Management
        1. 7.3.4.1 Narrow VDC Architecture
        2. 7.3.4.2 Dynamic Power Management
          1. 7.3.4.2.1 Input Current Limit on ILIM Pin
        3. 7.3.4.3 High Impedance (HIZ) Mode
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Thermistor Qualification
          1. 7.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 7.3.5.4.2 TS Pin Thermistor Configuration
          3. 7.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 7.3.5.4.4 JEITA Charge Rate Scaling
          5. 7.3.5.4.5 TS_BIAS Pin
        5. 7.3.5.5 Charging Safety Timers
      6. 7.3.6  USB On-The-Go (OTG)
        1. 7.3.6.1 Boost OTG Mode
      7. 7.3.7  Integrated 12-bit ADC for Monitoring
      8. 7.3.8  Status Outputs (INT , PG , STAT)
        1. 7.3.8.1 PG Pin Power Good Indicator
        2. 7.3.8.2 Charging Status Indicator (STAT)
        3. 7.3.8.3 Interrupt to Host (INT)
      9. 7.3.9  BATFET Control
        1. 7.3.9.1 Shutdown Mode
        2. 7.3.9.2 Ultra-Low Power Mode
        3. 7.3.9.3 System Power Reset
      10. 7.3.10 Protections
        1. 7.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 7.3.10.1.1 Battery Overcurrent Protection
          2. 7.3.10.1.2 Battery Undervoltage Lockout
        2. 7.3.10.2 Voltage and Current Monitoring in Forward Mode
          1. 7.3.10.2.1 Input Overvoltage
          2. 7.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 7.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 7.3.10.2.4 System Short
          5. 7.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 7.3.10.2.6 Sleep and Poor Source Comparators
        3. 7.3.10.3 Voltage and Current Monitoring in Reverse Mode
          1. 7.3.10.3.1 Boost Mode Overvoltage Protection
          2. 7.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 7.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 7.3.10.3.4 Boost Mode Battery Undervoltage
          5. 7.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 7.3.10.3.6 Boost Mode SYS Short
        4. 7.3.10.4 Thermal Regulation and Thermal Shutdown
          1. 7.3.10.4.1 Thermal Protection in Buck Mode
          2. 7.3.10.4.2 Thermal Protection in Boost Mode
          3. 7.3.10.4.3 Thermal Protection in Battery-only Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 START and STOP Conditions
        3. 7.5.1.3 Byte Format
        4. 7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.5.1.5 Target Address and Data Direction Bit
        6. 7.5.1.6 Single Write and Read
        7. 7.5.1.7 Multi-Write and Multi-Read
    6. 7.6 BQ25638 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YBG|30
散热焊盘机械数据 (封装 | 引脚)

6.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IQ_BAT Quiescent battery current (BAT, SYS, SW) when the charger is in the battery only mode, BATFET is enabled, ADC is disabled VBAT = 4V, No VBUS, BATFET is enabled, I2C enabled, ADC disabled, system is powered by battery. -40 °C < TJ < 60 °C 1.5 3 µA
IQ_BAT_ADC Quiescent battery current (BAT, SYS, SW) when the charger is in the battery only mode, BATFET is enabled, ADC is enabled VBAT = 4V, No VBUS, BATFET is enabled, I2C enabled, ADC enabled, system is powered by battery. -40 °C < TJ < 60 °C 260 µA
IQ_BAT_SD Quiescent battery current (BAT) when the charger is in shutdown mode, BATFET is disabled, ADC is disabled VBAT = 4V, No VBUS, BATFET is disabled, I2C disabled, in shutdown mode, ADC disabled, TJ < 60 °C 100 200 nA
IQ_BAT_ULPM Quiescent battery current (BAT) when the charger is in ultra low power mode, BATFET is disabled, ADC is disabled VBAT = 4V, No VBUS, BATFET is disabled, I2C disabled, in ultra low power mode, ADC disabled, TJ < 60 °C 1.3 µA
IQ_VBUS Quiescent input current (VBUS) VBUS = 5V, VBAT = 4V, charge disabled, converter switching, ISYS = 0A, PFM enabled 450 µA
ISD_VBUS Quiescent input current (VBUS) in HIZ VBUS = 5V, VBAT = 4V, HIZ mode, ADC disabled 5 20 µA
VBUS = 15V, VBAT = 4V, HIZ mode, ADC disabled 20 35 µA
IQ_OTG Quiescent battery current (BAT, SYS, SW) in boost OTG mode VBAT = 4V, VBUS = 5V, OTG mode enabled, converter switching, PFM enabled, IVBUS = 0A, TS float, TS_IGNORE = 1 250 µA
IQ_OTG Quiescent battery current (BAT, SYS, SW) in boost OTG mode VBAT = 4V, VBUS = 5V, OTG mode enabled, converter switching, PFM enabled, IVBUS = 0A 220 µA
VBUS / VBAT SUPPLY
VVBUS_OP VBUS operating range 3.9 18 V
VVBUS_UVLO VBUS falling to turn off I2C, no battery VBUS falling 3.0 3.15 3.3 V
VVBUS_UVLOZ VBUS rising for active I2C, no battery VBUS rising 3.2 3.35 3.5 V
VVBUS_OVP VBUS overvoltage rising threshold VBUS rising, VBUS_OVP = 0 6.1 6.5 6.7 V
VBUS rising, VBUS_OVP = 1 18.2 18.5 18.8 V
VVBUS_OVPZ VBUS overvoltage falling threshold VBUS falling, VBUS_OVP = 0 5.8 6.0 6.2 V
VBUS falling, VBUS_OVP = 1 17.6 17.8 18.3 V
VSLEEP Sleep mode falling threshold (VBUS - VBAT), VBUS falling 9 45 85 mV
VSLEEPZ Sleep mode rising threshold (VBUS - VBAT), VBUS rising 115 220 340 mV
VBAT_UVLOZ BAT voltage for active I2C, turn on BATFET, no VBUS VBAT rising 2.3 2.4 2.5 V
VBAT_UVLO BAT voltage to turnoff I2C, turn off BATFET, no VBUS VBAT falling, VBAT_UVLO = 0 2.1 2.2 2.3 V
VBAT falling, VBAT_UVLO = 1 1.7 1.8 1.9 V
VBAT_OTG BAT voltage rising threshold to enable OTG mode VBAT rising, VBAT_OTG_MIN = 0 2.9 3.0 3.1 V
VBAT rising, VBAT_OTG_MIN = 1 2.5 2.6 2.7 V
VBAT_OTGZ BAT voltage falling threshold to disable OTG mode VBAT falling, VBAT_OTG_MIN = 0 2.7 2.8 2.9 V
VBAT falling, VBAT_OTG_MIN = 1 2.3 2.4 2.5 V
VPOORSRC Bad adapter detection threshold VBUS falling 3.6 3.7 3.75 V
IPOORSRC Bad adapter detection current source 10 mA
POWER-PATH MANAGEMENT
VSYS_REG_ACC Typical system voltage regulation ISYS = 0A, VBAT > VSYSMIN, Charge Disabled. Offset above VBAT 50 mV
ISYS = 0A, VBAT < VSYSMIN, Charge Disabled. Offset above VSYSMIN 230 mV
VSYSMIN_RNG VSYSMIN register range 2.56 3.84 V
VSYSMIN_REG_STEP VSYSMIN register step size 80 mV
VSYSMIN_REG_ACC Minimum DC system voltage output ISYS = 0A, VBAT < VSYSMIN = B00h (3.52V), Charge Disabled 3.52 3.75 V
VSYS_SHORT VSYS short voltage falling threshold to enter forced PFM 0.9 V
VSYS_SHORTZ VSYS short voltage rising threshold to exit forced PFM 1.1 V
BATTERY CHARGER
VREG_RANGE Typical charge voltage regulation range 3.50 4.80 V
VREG_STEP Typical charge voltage step 10 mV
VREG_ACC Charge voltage accuracy TJ = 25°C –0.3 0.3 %
TJ = 0°C - 65°C –0.5 0.5 %
ICHG_RANGE Typical charge current regulation range 0.08 5.04 A
ICHG_STEP Typical charge current regulation step 80 mA
ICHG_ACC Typical charge current accuracy VBAT = 3.1V or 3.8V, ICHG = 1760mA –5 5 %
VBAT = 3.1V or 3.8V, ICHG = 1040mA –6 6 %
VBAT = 3.1V or 3.8V, ICHG = 480mA –10 10 %
IPRECHG_RANGE Typical pre-charge current range 40 1000 mA
IPRECHG_STEP Typical pre-charge current step 20 mA
IPRECHG_ACC Pre-charge current accuracy when VBAT below VSYSMIN setting VBAT = 2.5V, IPRECHG = 480mA –10 10 %
VBAT = 2.5V, IPRECHG = 200mA –10 10 %
VBAT = 2.5V, IPRECHG = 100mA –30 30 %
VBAT = 2.5V, IPRECHG = 40mA –70 70 %
ITERM_RANGE Typical termination current range 30 1000 mA
ITERM_STEP Typical termination current step 10 mA
ITERM_ACC Termination current accuracy ITERM = 30mA –70 70 %
ITERM = 100mA –15 15 %
ITERM = 200mA –10 10 %
VBAT_SHORTZ Battery short voltage rising threshold to start pre-charge VBAT rising 2.25 V
VBAT_SHORT Battery short voltage falling threshold to stop pre-charge VBAT falling, VBAT_UVLO=0 2.05 V
VBAT_SHORT Battery short voltage falling threshold to stop pre-charge VBAT falling, VBAT_UVLO=1 1.85 V
IBAT_SHORT Battery short trickle charging current VBAT < VBAT_SHORTZ, ITRICKLE = 0 6 20 34 mA
VBAT < VBAT_SHORTZ, ITRICKLE = 1  64 80 102 mA
VBAT_LOWV Battery LOW rising voltage threshold to start fast charge BATLOWV = 3.0V 2.9 3.0 3.1 V
Battery LOW falling voltage threshold to start fast charge BATLOWV = 3.0V 2.7 2.8 2.9 V
VRECHG Battery recharge threshold below VREG VBAT falling, VRECHG = 0 100 mV
VBAT falling, VRECHG = 1 200 mV
IPMID_LOAD PMID discharge load current 20 mA
IBAT_LOAD Battery discharge load current 20 mA
ISYS_LOAD System discharge load current 20 mA
BATFET
VSUPPZ SYS < BAT threshold to exit supplement mode 5 mV
RBATFET MOSFET on resistance from SYS to BAT 7 12 mΩ
BATTERY PROTECTIONS
VBAT_OVP Battery overvoltage rising threshold As percentage of VREG 103 104 105 %
VBAT_OVPZ Battery overvoltage falling threshold As percentage of VREG 101 102 103 %
IBATFET_OCP BATFET over-current rising threshold 7 A
IBAT_PK Battery discharging peak current rising threshold IBAT_PK = 00 3 A
IBAT_PK = 01 6 A
IBAT_PK = 10 9 A
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Typical input voltage regulation range 3.8 16.8 V
VINDPM_STEP Typical input voltage regulation step 40 mV
VINDPM_ACC Input voltage regulation accuracy VINDPM=4.6V –3 3 %
VINDPM=8V –3 3 %
VINDPM=16V –2 2 %
VINDPM_BAT_TRACK Battery tracking VINDPM accuracy VBAT = 3.9V, VINDPM_BAT_TRACK=1, VINDPM = 4V 4.1 4.25 4.4 V
IINDPM_RANGE Typical input current regulation range 0.1 3.2 A
IINDPM_STEP Typical input current regulation step 20 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 500mA, VBUS=5V 450 475 500 mA
IINDPM = 900mA, VBUS=5V 750 825 900 mA
IINDPM = 1500mA, VBUS=5V 1350 1425 1500 mA
KILIM ILIM Pin Scale Factor, IINREG = KILIM / RILIM INREG = 1.5 A 3000 3333 3666 AΩ
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy TREG = 1 120 °C
TREG = 0 60 °C
TSHUT Thermal Shutdown Rising Threshold Temperature Increasing 150 °C
TSHUT_HYS Thermal Shutdown Falling Hysteresis Temperature Decreasing by TSHUT_HYS 30 °C
THERMISTOR COMPARATORS (CHARGE MODE)
VTS_COLD TS pin rising voltage threshold for TH1 comparator to transition from TS_COOL to TS_COLD. As Percentage to TS pin bias reference (–5°C w/ 103AT), TS_TH1 = 0 74.75 75.25 75.75 %
As Percentage to TS pin bias reference (0°C w/ 103AT), TS_TH1 = 1 72.75 73.25 73.75 %
VTS_COLDZ TS pin falling voltage threshold for TH1 comparator to transition from TS_COLD to TS_COOL. As Percentage to TS pin bias reference (–2.5°C w/ 103AT), TS_TH1 = 0 73.75 74.25 74.75 %
As Percentage to TS pin bias reference (2.5°C w/ 103AT), TS_TH1 = 1 71.75 72.25 72.75 %
VTS_COOL TS pin rising voltage threshold for TH2 comparator to transition from TS_PRECOOL to TS_COOL. As Percentage to TS pin bias reference (5°C w/ 103AT), TS_TH2 = 0 70.5 70.75 71.25 %
As Percentage to TS pin bias reference (7.5°C w/ 103AT), TS_TH2 = 1 67.25 69.75 70.25 %
As Percentage to TS pin bias reference (10°C w/ 103AT), TS_TH2 = 2 67.75 68.25 68.75 %
As Percentage to TS pin bias reference (12.5°C w/ 103AT), TS_TH2 = 3 65.25 66.25 66.75 %
VTS_COOLZ TS pin falling voltage threshold for TH2 comparator to transition from TS_COOL to TS_PRECOOL. As Percentage to TS pin bias reference (7.5°C w/ 103AT), TS_TH2 = 0 67.25 69.75 70.25 %
As Percentage to TS pin bias reference (10°C w/ 103AT), TS_TH2 = 1 67.75 68.25 68.75 %
As Percentage to TS pin bias reference (12.5°C w/ 103AT), TS_TH2 = 2 65.25 66.25 66.75 %
As Percentage to TS pin bias reference (15°C w/ 103AT), TS_TH2 = 3 64.75 65.25 65.75 %
VTS_PRECOOL TS pin rising voltage threshold for TH3 comparator to transition from TS_NORMAL to TS_PRECOOL. As Percentage to TS pin bias reference (15°C w/ 103AT), TS_TH3 = 0 64.75 65.25 65.75 %
As Percentage to TS pin bias reference (17.5°C w/ 103AT), TS_TH3 = 1 63.75 64.25 64.75 %
As Percentage to TS pin bias reference (20°C w/ 103AT), TS_TH3 = 2 61.75 62.25 62.75 %
As Percentage to TS pin bias reference (22.5°C w/ 103AT), TS_TH3 = 3 60.25 60.75 61.25 %
VTS_PRECOOLZ TS pin falling voltage threshold for TH3 comparator to transition from TS_PRECOOL to TS_NORMAL. As Percentage to TS pin bias reference (17.5°C w/ 103AT), TS_TH3 =0 63.75 64.25 64.75 %
As Percentage to TS pin bias reference (20°C w/ 103AT), TS_TH3 = 1 61.75 62.25 62.75 %
As Percentage to TS pin bias reference (22.5°C w/ 103AT), TS_TH3 = 2 60.25 60.75 61.25 %
As Percentage to TS pin bias reference (25°C w/ 103AT), TS_TH3 = 3 58.5 59.00 59.5 %
VTS_PREWARM TS pin falling voltage threshold for TH4 comparator to transition from TS_NORMAL to TS_PREWARM. As Percentage to TS pin bias reference (32.5°C w/ 103AT), TS_TH4 = 0 53.25 53.75 54.25 %
As Percentage to TS pin bias reference (35°C w/ 103AT), TS_TH4 = 1 51.50 52.00 52.50 %
As Percentage to TS pin bias reference (37.5°C w/ 103AT), TS_TH4 = 2 50.00 50.50 51.00 %
As Percentage to TS pin bias reference (40°C w/ 103AT), TS_TH4 = 3 47.75 48.25 48.75 %
VTS_PREWARMZ TS pin rising voltage threshold for TH4 comparator to transition from TS_PREWARM to TS_NORMAL. As Percentage to TS pin bias reference (30°C w/ 103AT), TS_TH4 = 0 55.00 55.50 56.00 %
As Percentage to TS pin bias reference (32.5°C w/ 103AT), TS_TH4 = 1 53.25 53.75 54.25 %
As Percentage to TS pin bias reference (35°C w/ 103AT), TS_TH4 = 2 51.50 52.00 52.50 %
As Percentage to TS pin bias reference (37.5°C w/ 103AT), TS_TH4 = 3 50.00 50.50 51.00 %
VTS_WARM TS pin falling voltage threshold for TH5 comparator to transition from TS_PREWARM to TS_WARM. As Percentage to TS pin bias reference (42.5°C w/ 103AT), TS_TH5 = 0 46.25 46.75 47.25 %
As Percentage to TS pin bias reference (45°C w/ 103AT), TS_TH5 = 1 44.25 44.75 45.25 %
As Percentage to TS pin bias reference (47.5°C w/ 103AT), TS_TH5 = 2 42.50 43.00 43.50 %
As Percentage to TS pin bias reference (50°C w/ 103AT), TS_TH5 = 3 40.75 41.25 41.75 %
VTS_WARMZ TS pin rising voltage threshold for TH5 comparator to transition from TS_WARM to TS_PREWARM. As Percentage to TS pin bias reference (40°C w/ 103AT), TS_TH5 = 0 47.75 48.25 48.75 %
As Percentage to TS pin bias reference (42.5°C w/ 103AT), TS_TH5 = 1 46.25 46.75 47.25 %
As Percentage to TS pin bias reference (45°C w/ 103AT), TS_TH5 = 2 44.25 44.75 45.25 %
As Percentage to TS pin bias reference (47.5°C w/ 103AT), TS_TH5 = 3 42.50 43.00 43.50 %
VTS_HOT TS pin falling voltage threshold for TH6 comparator to transition from TS_WARM to TS_HOT. As Percentage to TS pin bias reference (55°C w/ 103AT), TS_TH6 = 0 37.25 37.75 38.25 %
As Percentage to TS pin bias reference (60°C w/ 103AT), TS_TH6 = 1  34.00 34.50 35.00 %
VTS_HOTZ TS pin rising voltage threshold for TH6 comparator to transition from TS_HOT to TS_WARM. As Percentage to TS pin bias reference (52.5°C w/ 103AT), TS_TH6 = 0 39.25 39.75 40.25 %
As Percentage to TS pin bias reference (57.5°C w/ 103AT), TS_TH6 = 1 35.75 36.25 36.75 %
THERMISTOR COMPARATORS (OTG MODE)
VTS_OTG_COLD TS pin rising voltage threshold to transition from TS_OTG_NORMAL to TS_OTG_COLD. As Percentage to TS pin bias reference (–20°C w/ 103AT), TS_TH_OTG_COLD = 0 79.50 80.00 80.50 %
As Percentage to TS pin bias reference (–10°C w/ 103AT), TS_TH_OTG_COLD = 1 76.50 77.00 77.50 %
VTS_OTG_COLDZ TS pin falling voltage threshold to transition from TS_OTG_COLD to TS_OTG_NORMAL. As Percentage to TS pin bias reference (–15°C w/ 103AT), TS_TH_OTG_COLD = 0 78.00 78.50 79.00 %
As Percentage to TS pin bias reference (–5°C w/ 103AT), TS_TH_OTG_COLD = 1 74.75 75.25 75.75 %
VTS_OTG_HOT TS pin falling voltage threshold to transition from TS_OTG_NORMAL to TS_OTG_HOT. As Percentage to TS pin bias reference (55°C w/ 103AT), TS_OTG_HOT = 00 37.25 37.75 38.25 %
As Percentage to TS pin bias reference (60°C w/ 103AT), TS_OTG_HOT = 01 34.00 34.50 35.00 %
As Percentage to TS pin bias reference (65°C w/ 103AT), TS_OTG_HOT = 10 30.75 31.25 31.75 %
VTS_OTG_HOTZ TS pin rising voltage threshold to transition from TS_OTG_HOT to TS_OTG_NORMAL. As Percentage to TS pin bias reference (52.5°C w/ 103AT), TS_OTG_HOT = 00 39.25 39.75 40.25 %
As Percentage to TS pin bias reference (57.5°C w/ 103AT), TS_OTG_HOT = 01 35.75 36.25 36.75 %
As Percentage to TS pin bias reference (62.5°C w/ 103AT), TS_OTG_HOT = 10 32.50 33.00 33.50 %
SWITCHING CONVERTER
FSW PWM switching frequency Oscillator frequency 1.35 1.5 1.65 MHz
MOSFET TURN-ON RESISTANCE
RQ1_ON VBUS to PMID on resistance Tj = –40°C-85°C (typical value is under 25°C) 15 20 mΩ
RQ2_ON Buck high-side switching MOSFET turn on resistance between PMID and SW Tj = –40°C-85°C (typical value is under 25°C) 20 27 mΩ
RQ3_ON Buck low-side switching MOSFET turn on resistance between SW and PGND Tj = –40°C-85°C (typical value is under 25°C) 16 20 mΩ
OTG MODE CONVERTER
VOTG_RANGE Typical OTG mode voltage regulation range 3.8 9.6 V
VOTG_STEP Typical OTG mode voltage regulation step 80 mV
VOTG_ACC OTG mode voltage regulation accuracy IVBUS = 0A, VOTG = 9V –2 2 %
VOTG_ACC OTG mode voltage regulation accuracy IVBUS = 0A, VOTG = 5V –3 3 %
IOTG_RANGE Typical OTG mode current regulation range 0.1 3.2 A
IOTG_STEP Typical OTG mode current regulation step 20 mA
IOTG_ACC OTG mode current regulation accuracy IOTG = 1.8A –3 3 %
IOTG = 1.5A –5 5 %
IOTG = 1.0A –10 10 %
VOTG_UVP OTG mode undervoltage falling threshold at PMID 3.4 V
REGN LDO
VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.4 4.6 V
VVBUS = 9V, IREGN = 20mA 4.8 5.0 5.2 V
VREGNZ_OK REGN not good falling threshold Converter switching 3.2 V
Converter not switching 2.3 V
IREGN_LIM REGN LDO current limit VVBUS = 5V, VREGN = 4.3V 20 mA
ITS_BIAS_FAULT Rising threshold to transition from TSBIAS good condition to fault condition REGN=5V; ISINK applied on TS_BIAS pin 2.5 4.5 8 mA
ITS_BIAS_FAULTZ Falling threshold to transition from TSBIAS fault condition to good condition REGN=5V; ISINK applied on TS_BIAS pin 2 3.85 7 mA
PG THRESHOLD
PG_TH VBUS voltage falling threshold to release PG pin pulldown PG_TH = 000b 3.7 V
PG_TH = 001b 7.4 V
PG_TH = 010b 8.0 V
PG_TH = 011b 10.4 V
PG_TH = 100b 11.0 V
PG_TH = 101b 13.4 V
PG_TH = 110b 14.0 V
PG_TH = 111b 13.7 V
PG_THz VBUS voltage rising threshold to enable PG pin pulldown PG_TH = 000b 3.9 V
PG_TH = 001b 7.9 V
PG_TH = 010b 8.5 V
PG_TH = 011b 10.9 V
PG_TH = 100b 11.5 V
PG_TH = 101b 13.9 V
PG_TH = 110b 14.5 V
PG_TH = 111b 14.2 V
ADC MEASUREMENT ACCURACY AND PERFORMANCE
tADC_CONV Conversion-time, Each Measurement ADC_SAMPLE = 00 24 ms
ADC_SAMPLE = 01 12 ms
ADC_SAMPLE = 10 6 ms
ADC_SAMPLE = 11 3 ms
ADC_RES Effective Resolution ADC_SAMPLE = 00 11 12 bits
ADC_SAMPLE = 01 10 11 bits
ADC_SAMPLE = 10 9 10 bits
ADC_SAMPLE = 11 8 9 bits
ADC MEASUREMENT RANGE AND LSB
IBUS_ADC ADC Bus Current Reading (both forward and OTG) Range –5 5 A
LSB 2.5 mA
VBUS_ADC ADC VBUS Voltage Reading Range 0 20 V
LSB 5 mV
VPMID_ADC ADC PMID Voltage Reading Range 0 20 V
LSB 5 mV
VBAT_ADC ADC BAT Voltage Reading Range 0 5 V
LSB 1.25 mV
VBAT_ADC ADC BAT Voltage Reading Accuracy Accuracy @ 4V, ADC_SAMPLE = 00 –0.5 0.5 %
VSYS_ADC ADC SYS Voltage Reading Range 0 5 V
LSB 1.25 mV
IBAT_ADC ADC BAT Current Reading Range –10 5 A
LSB 5 mA
TS_ADC ADC TS Voltage Reading Range as a percent of REGN 0 99.9 %
ADC TS Voltage Reading LSB 0.098 %
TDIE_ADC ADC Die Temperature Reading Range –40 150 °C
LSB 0.5 °C
ADCIN_ADC ADC ADCIN Voltage Reading Range 0 1 V
ADCIN_ADC ADC ADCIN Voltage Reading LSB 0.25 mV
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SDA and SCL 0.78 V
VIL Input low threshold level, SDA and SCL 0.42 V
VOL_SDA Output low threshold level Sink current = 5mA, 1.2V VDD 0.3 V
IBIAS High-level leakage current Pull up rail 1.8V 1 µA
LOGIC OUTPUT PIN (INT, PG, STAT)
VOL Output low threshold level Sink current = 5mA 0.3 V
IOUT_BIAS High-level leakage current Pull up rail 1.8V 1 µA
LOGIC INPUT PIN (CE, QON)
VIH_CE Input high threshold level, /CE 0.78 V
VIL_CE Input low threshold level, /CE 0.4 V
IIN_BIAS_CE High-level leakage current, /CE Pull up rail 1.8V 1 µA
VIH_QON Input high threshold level, /QON 1.3 V
VIL_QON Input low threshold level, /QON 0.4 V
VQON Internal /QON pull up /QON is pulled up to VAA internally 5 V
RQON Internal /QON pull up resistance 250 kΩ