ZHCSU23A October   2023  – December 2023 BQ25638

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 说明（续）
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On-Reset (POR)
      2. 7.3.2  Device Power Up from Battery
      3. 7.3.3  Device Power Up from Input Source
        1. 7.3.3.1 REGN LDO Power Up
        2. 7.3.3.2 Poor Source Qualification
        3. 7.3.3.3 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        4. 7.3.3.4 Converter Power-Up
        5. 7.3.3.5 Input Current Optimizer (ICO)
        6. 7.3.3.6 Switching Frequency and Dithering Feature
      4. 7.3.4  Power Path Management
        1. 7.3.4.1 Narrow VDC Architecture
        2. 7.3.4.2 Dynamic Power Management
          1. 7.3.4.2.1 Input Current Limit on ILIM Pin
        3. 7.3.4.3 High Impedance (HIZ) Mode
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Thermistor Qualification
          1. 7.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 7.3.5.4.2 TS Pin Thermistor Configuration
          3. 7.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 7.3.5.4.4 JEITA Charge Rate Scaling
          5. 7.3.5.4.5 TS_BIAS Pin
        5. 7.3.5.5 Charging Safety Timers
      6. 7.3.6  USB On-The-Go (OTG)
        1. 7.3.6.1 Boost OTG Mode
      7. 7.3.7  Integrated 12-bit ADC for Monitoring
      8. 7.3.8  Status Outputs (INT , PG , STAT)
        1. 7.3.8.1 PG Pin Power Good Indicator
        2. 7.3.8.2 Charging Status Indicator (STAT)
        3. 7.3.8.3 Interrupt to Host (INT)
      9. 7.3.9  BATFET Control
        1. 7.3.9.1 Shutdown Mode
        2. 7.3.9.2 Ultra-Low Power Mode
        3. 7.3.9.3 System Power Reset
      10. 7.3.10 Protections
        1. 7.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 7.3.10.1.1 Battery Overcurrent Protection
          2. 7.3.10.1.2 Battery Undervoltage Lockout
        2. 7.3.10.2 Voltage and Current Monitoring in Forward Mode
          1. 7.3.10.2.1 Input Overvoltage
          2. 7.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 7.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 7.3.10.2.4 System Short
          5. 7.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 7.3.10.2.6 Sleep and Poor Source Comparators
        3. 7.3.10.3 Voltage and Current Monitoring in Reverse Mode
          1. 7.3.10.3.1 Boost Mode Overvoltage Protection
          2. 7.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 7.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 7.3.10.3.4 Boost Mode Battery Undervoltage
          5. 7.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 7.3.10.3.6 Boost Mode SYS Short
        4. 7.3.10.4 Thermal Regulation and Thermal Shutdown
          1. 7.3.10.4.1 Thermal Protection in Buck Mode
          2. 7.3.10.4.2 Thermal Protection in Boost Mode
          3. 7.3.10.4.3 Thermal Protection in Battery-only Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 START and STOP Conditions
        3. 7.5.1.3 Byte Format
        4. 7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.5.1.5 Target Address and Data Direction Bit
        6. 7.5.1.6 Single Write and Read
        7. 7.5.1.7 Multi-Write and Multi-Read
    6. 7.6 BQ25638 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YBG|30
散热焊盘机械数据 (封装 | 引脚)

5 Pin Configuration and Functions

GUID-20230530-SS0I-PJS7-JZHJ-TSBF0BZCF3MP-low.svg Figure 5-1 BQ25638 Pinout, 30-Ball YBG DSBGA Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
ADCIN C5 AI External ADC Input – Connect an external analog signal up-to 1-V to monitor.
BAT E1 P Positive Terminal of Battery Pack Connection – The internal BATFET is connected between SYS and BAT. Connect a 10 µF ceramic capacitor closely to the BAT pin and GND.
E2
E3
BATP F1 AI Positive Battery Voltage Sense – Kelvin connect to positive battery terminal. Place 100 Ω series resistance between this pin and the battery positive terminal.
BTST B5 P PWM High-side Driver Supply – Internally, BTST is connected to the cathode of the boot-strap diode. Connect a 0.047 µF bootstrap capacitor from SW to BTST.
CE F2 DI Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating.
TS_BIAS F4 AO Bias for the TS Resistor Voltage Divider– Provides the bias voltage for the TS resistor voltage divider.
ILIM F3 AI Input Current Limit Setting Pin – ILIM pin sets the input current limit as IINREG = KILIM / RILIM, where RILIM is connected from ILIM pin to GND. The input current is limited to the lower of the two values set by ILIM pin and IINDPM register bits. The ILIM pin can also be used to monitor input current. The input current is proportional to the voltage on ILIM pin and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8 V). The ILIM pin function is disabled when EN_EXTILIM bit is set to 0.
INT F5 DO Open Drain Active Low Interrupt Output – Connect /INT to the logic rail via a 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to the host to report charger device status and fault.
PG C2 DO Open Drain Active Low Power Good Indicator – Connect to the pull up rail via a 2.2-kΩ resistor. LOW indicates a valid input source above PG_TH.
PGND A4 P Ground Return
B4
C4
PMID A2 P Blocking MOSFET Connection – Given the total input capacitance, place 1 µF on VBUS, and the rest on PMID, as close to the IC as possible. Typical value: 10 µF in parallel with 0.1 µF ceramic capacitor.
B2
QON D4 DI BATFET Enable or System Power Reset Control Input – If the charger is in ultra-low power mode, a logic low on this pin with tSM_EXIT duration forces the device to exit the mode. If the charger is not in ultra-low power mode, a logic low on this pin with tQON_RST initiates a full system power reset if either VVBUS < VVBUS_UVLO or BATFET_CTRL_WVBUS = 1. QON has no effect during shutdown mode. The pin contains an internal pull-up to maintain default high logic.
REGN A5 P Internal Linear Regulator Output – Internally, REGN is connected to the anode of the boot-strap diode. Connect a 10V or higher rating 4.7 µF ceramic capacitor from REGN to power ground. The capacitor should be close to the IC. The REGN LDO output is used for the internal MOSFETs gate driving voltage and for biasing the external TS pin thermistor in BQ25639.
SCL D5 DI I2C Interface Clock – Connect SCL to the logic rail through a 10 kΩ resistor.
SDA E5 DIO I2C Interface Data – Connect SDA to the logic rail through a 10 kΩ resistor.
STAT C1 DO Open Drain Charge Status Output – Indicates various charger operations. Connect to the pull up rail via a 2.2kΩ resistor. LOW indicates charging in progress. HIGH indicates charging completed or charging disabled. When any fault condition occurs, STAT pin blinks at 1Hz. Setting DIS_STAT = 1 will disable the STAT pin function, causing the pin to be pulled high. Leave floating if unused.
SW A3 P Switching Node Connecting to Output Inductor – Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 47 nF bootstrap capacitor from SW to BTST.
B3
C3
SYS D1 P Charger Output Voltage to System – Buck converter output connection point to the system. The internal BATFET is connected between SYS and BAT. Connect 20μF close to the SYS pin.
D2
D3
TS E4 AI Temperature Qualification Voltage Input – Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from TS pin bias reference to TS, then to GND. Charge suspends when TS pin voltage is out of range. Recommend a 103AT-2 10kΩ thermistor.
VBUS A1 P Charger Input Voltage – The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1 uF ceramic capacitor from VBUS to GND as close as possible to IC.
B1
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power