ZHCSLR7A March   2021  – October 2021 ADS7067

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
      2. 7.3.2  Reference
        1. 7.3.2.1 External Reference
        2. 7.3.2.2 Internal Reference
      3. 7.3.3  ADC Transfer Function
      4. 7.3.4  ADC Offset Calibration
      5. 7.3.5  Programmable Averaging Filters
      6. 7.3.6  CRC on Data Interface
      7. 7.3.7  Oscillator and Timing Control
      8. 7.3.8  Diagnostic Modes
        1. 7.3.8.1 Bit-Walk Test Mode
        2. 7.3.8.2 Fixed Voltage Test Mode
      9. 7.3.9  Output Data Format
        1. 7.3.9.1 Status Flags
        2. 7.3.9.2 Output CRC (Device to Host)
        3. 7.3.9.3 Input CRC (Host to Device)
      10. 7.3.10 Device Programming
        1. 7.3.10.1 Enhanced-SPI Interface
        2. 7.3.10.2 Daisy-Chain Mode
        3. 7.3.10.3 Register Read/Write Operation
          1. 7.3.10.3.1 Register Write
          2. 7.3.10.3.2 Register Read
            1. 7.3.10.3.2.1 Register Read With CRC
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power-Up and Reset
      2. 7.4.2 Manual Mode
      3. 7.4.3 On-the-Fly Mode
      4. 7.4.4 Auto-Sequence Mode
    5. 7.5 ADS7067 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Charge-Kickback Filter and ADC Amplifier
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 AVDD and DVDD Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.5 ADS7067 Registers

Table 7-9 lists the ADS7067 registers. All register offset addresses not listed in Table 7-9 should be considered as reserved locations and the register contents should not be modified.

Table 7-9 ADS7067 Registers
Address Acronym Register Name Section
0x0 SYSTEM_STATUS #ADS7067_ADS7067_ADS7067_SYSTEM_STATUS
0x1 GENERAL_CFG #ADS7067_ADS7067_ADS7067_GENERAL_CFG
0x2 DATA_CFG #ADS7067_ADS7067_ADS7067_DATA_CFG
0x3 OSR_CFG #ADS7067_ADS7067_ADS7067_OSR_CFG
0x4 OPMODE_CFG #ADS7067_ADS7067_ADS7067_OPMODE_CFG
0x5 PIN_CFG #ADS7067_ADS7067_ADS7067_PIN_CFG
0x7 GPIO_CFG #ADS7067_ADS7067_ADS7067_GPIO_CFG
0x9 GPO_DRIVE_CFG #ADS7067_ADS7067_ADS7067_GPO_DRIVE_CFG
0xB GPO_OUTPUT_VALUE #ADS7067_ADS7067_ADS7067_GPO_OUTPUT_VALUE
0xD GPI_VALUE #ADS7067_ADS7067_ADS7067_GPI_VALUE
0x10 SEQUENCE_CFG #ADS7067_ADS7067_ADS7067_SEQUENCE_CFG
0x11 CHANNEL_SEL #ADS7067_ADS7067_ADS7067_CHANNEL_SEL
0x12 AUTO_SEQ_CH_SEL #ADS7067_ADS7067_ADS7067_AUTO_SEQ_CH_SEL
0xBF DIAGNOSTICS_KEY #ADS7067_ADS7067_ADS7067_DIAGNOSTICS_KEY
0xC0 DIAGNOSTICS_EN #ADS7067_ADS7067_ADS7067_DIAGNOSTICS_EN
0xC1 BIT_SAMPLE_LSB #ADS7067_ADS7067_ADS7067_BIT_SAMPLE_LSB
0xC2 BIT_SAMPLE_MSB #ADS7067_ADS7067_ADS7067_BIT_SAMPLE_MSB

Complex bit access types are encoded to fit into small table cells. Table 7-10 shows the codes that are used for access types in this section.

Table 7-10 ADS7067 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
- n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y When this variable is used in a register name, an offset, or an address it refers to the value of a register array.

7.5.1 SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]

SYSTEM_STATUS is shown in Figure 7-16 and described in Table 7-11.

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Figure 7-16 SYSTEM_STATUS Register
7 6 5 4 3 2 1 0
RSVD SEQ_STATUS RESERVED CRCERR_FUSE CRCERR_IN BOR
R-1b R-0b R-0b R-0b R/W-0b R/W-1b
Table 7-11 SYSTEM_STATUS Register Field Descriptions
Bit Field Type Reset Description
7 RSVD R 1b Reads return 1b.
6 SEQ_STATUS R 0b Status of the channel sequencer.
0b = Sequence stopped
1b = Sequence in progress
5-3 RESERVED R 0b Reserved Bit
2 CRCERR_FUSE R 0b Device power-up configuration CRC check status. To re-evaluate this bit, software reset the device or power cycle AVDD.
0b = No problems detected in power-up configuration.
1b = Device configuration not loaded correctly.
1 CRCERR_IN R/W 0b Status of CRC check on incoming data. Write 1b to clear this error flag.
0b = No CRC error.
1b = CRC error detected. All register writes, except to addresses 0x00 and 0x01, are blocked.
0 BOR R/W 1b Brown out reset indicator. This bit is set if brown out condition occurs or device is power cycled. Write 1b to this bit to clear the flag.
0b = No brown out since last time this bit was cleared.
1b = Brown out condition detected or device power cycled.

7.5.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0]

GENERAL_CFG is shown in Figure 7-17 and described in Table 7-12.

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Figure 7-17 GENERAL_CFG Register
7 6 5 4 3 2 1 0
REF_EN CRC_EN RESERVED RANGE CH_RST CAL RST
R/W-0b R/W-0b R-0b R/W-0b R/W-0b R/W-0b W-0b
Table 7-12 GENERAL_CFG Register Field Descriptions
Bit Field Type Reset Description
7 REF_EN R/W 0b Enable or disable the internal reference.
0b = Internal reference is powered down.
1b = Internal reference is enabled.
6 CRC_EN R/W 0b Enable or disable the CRC on device interface.
0b = CRC module disabled.
1b = CRC appended to data output. CRC check is enabled on incoming data.
5-4 RESERVED R 0b Reserved Bit
3 RANGE R/W 0b Select the input range of the ADC.
0b = Input range of the ADC is 1x VREF
1b = Input range of the ADC is 2x VREF
2 CH_RST R/W 0b Force all channels to be analog inputs.
0b = Normal operation
1b = All channels will be set as analog inputs irrespective of configuration in other registers
1 CAL R/W 0b Calibrate ADC offset.
0b = Normal operation.
1b = ADC offset is calibrated. After calibration is complete, this bit is set to 0b.
0 RST W 0b Software reset all registers to default values.
0b = Normal operation.
1b = Device is reset. After reset is complete, this bit is set to 0b and BOR bit is set to 1b.

7.5.3 DATA_CFG Register (Address = 0x2) [reset = 0x0]

DATA_CFG is shown in Figure 7-18 and described in Table 7-13.

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Figure 7-18 DATA_CFG Register
7 6 5 4 3 2 1 0
FIX_PAT RESERVED APPEND_STATUS[1:0] RESERVED CPOL_CPHA[1:0]
R/W-0b R-0b R/W-0b R-0b R/W-0b
Table 7-13 DATA_CFG Register Field Descriptions
Bit Field Type Reset Description
7 FIX_PAT R/W 0b Device outputs fixed data bits which can be helpful for debugging communication with the device.
0b = Normal operation.
1b = Device outputs fixed code 0xA5A5 repeatitively when reading ADC data.
6 RESERVED R 0b Reserved Bit
5-4 APPEND_STATUS[1:0] R/W 0b Append 4-bit channel ID or status flags to output data.
0b = Channel ID and status flags are not appended to ADC data.
1b = 4-bit channel ID is appended to ADC data.
10b = 4-bit status flags are appended to ADC data.
11b = Reserved.
3-2 RESERVED R 0b Reserved Bit
1-0 CPOL_CPHA[1:0] R/W 0b This field sets the polarity and phase of SPI communication.
0b = CPOL = 0, CPHA = 0.
1b = CPOL = 0, CPHA = 1.
10b = CPOL = 1, CPHA = 0.
11b = CPOL = 1, CPHA = 1.

7.5.4 OSR_CFG Register (Address = 0x3) [reset = 0x0]

OSR_CFG is shown in Figure 7-19 and described in Table 7-14.

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Figure 7-19 OSR_CFG Register
7 6 5 4 3 2 1 0
RESERVED OSR[2:0]
R-0b R/W-0b
Table 7-14 OSR_CFG Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 0b Reserved Bit
2-0 OSR[2:0] R/W 0b Selects the oversampling ratio for ADC conversion result.
0b = No averaging
1b = 2 samples
10b = 4 samples
11b = 8 samples
100b = 16 samples
101b = 32 samples
110b = 64 samples
111b = 128 samples

7.5.5 OPMODE_CFG Register (Address = 0x4) [reset = 0x1]

OPMODE_CFG is shown in Figure 7-20 and described in Table 7-15.

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Figure 7-20 OPMODE_CFG Register
7 6 5 4 3 2 1 0
RESERVED OSC_SEL CLK_DIV[3:0]
R-0b R/W-0b R/W-1b
Table 7-15 OPMODE_CFG Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 0b Reserved Bit
4 OSC_SEL R/W 0b Selects the oscillator for internal timing generation.
0b = High-speed oscillator.
1b = Low-power oscillator.
3-0 CLK_DIV[3:0] R/W 1b Sampling speed control when using averaging filters. Refer to section on oscillator and timing control for details.

7.5.6 PIN_CFG Register (Address = 0x5) [reset = 0x0]

PIN_CFG is shown in Figure 7-21 and described in Table 7-16.

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Figure 7-21 PIN_CFG Register
7 6 5 4 3 2 1 0
PIN_CFG[7:0]
R/W-0b
Table 7-16 PIN_CFG Register Field Descriptions
Bit Field Type Reset Description
7-0 PIN_CFG[7:0] R/W 0b Configure device channels AIN/GPIO [7:0] as analog inputs or GPIOs.
0b = Channel is configured as analog input.
1b = Channel is configured as GPIO.

7.5.7 GPIO_CFG Register (Address = 0x7) [reset = 0x0]

GPIO_CFG is shown in Figure 7-22 and described in Table 7-17.

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Figure 7-22 GPIO_CFG Register
7 6 5 4 3 2 1 0
GPIO_CFG[7:0]
R/W-0b
Table 7-17 GPIO_CFG Register Field Descriptions
Bit Field Type Reset Description
7-0 GPIO_CFG[7:0] R/W 0b Configure GPIO[7:0] as either digital inputs or digital outputs.
0b = GPIO is configured as digital input.
1b = GPIO is configured as digital output.

7.5.8 GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]

GPO_DRIVE_CFG is shown in Figure 7-23 and described in Table 7-18.

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Figure 7-23 GPO_DRIVE_CFG Register
7 6 5 4 3 2 1 0
GPO_DRIVE_CFG[7:0]
R/W-0b
Table 7-18 GPO_DRIVE_CFG Register Field Descriptions
Bit Field Type Reset Description
7-0 GPO_DRIVE_CFG[7:0] R/W 0b Configure digital outputs GPO[7:0] as open-drain or push-pull outputs.
0b = Digital output is open-drain; connect external pullup resistor.
1b = Push-pull driver is used for digital output.

7.5.9 GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]

GPO_OUTPUT_VALUE is shown in Figure 7-24 and described in Table 7-19.

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Figure 7-24 GPO_OUTPUT_VALUE Register
7 6 5 4 3 2 1 0
GPO_OUTPUT_VALUE[7:0]
R/W-0b
Table 7-19 GPO_OUTPUT_VALUE Register Field Descriptions
Bit Field Type Reset Description
7-0 GPO_OUTPUT_VALUE[7:0] R/W 0b Logic level to be set on digital outputs GPO[7:0].
0b = Digital output set to logic 0.
1b = Digital output set to logic 1.

7.5.10 GPI_VALUE Register (Address = 0xD) [reset = 0x0]

GPI_VALUE is shown in Figure 7-25 and described in Table 7-20.

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Figure 7-25 GPI_VALUE Register
7 6 5 4 3 2 1 0
GPI_VALUE[7:0]
R-0b
Table 7-20 GPI_VALUE Register Field Descriptions
Bit Field Type Reset Description
7-0 GPI_VALUE[7:0] R 0b Readback the logic level on GPIO[7:0].
0b = GPIO is at logic 0.
1b = GPIO is at logic 1.

7.5.11 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]

SEQUENCE_CFG is shown in Figure 7-26 and described in Table 7-21.

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Figure 7-26 SEQUENCE_CFG Register
7 6 5 4 3 2 1 0
RESERVED SEQ_START RESERVED SEQ_MODE[1:0]
R-0b R/W-0b R-0b R/W-0b
Table 7-21 SEQUENCE_CFG Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 0b Reserved Bit
4 SEQ_START R/W 0b Control for start of channel sequence when using auto sequence mode (SEQ_MODE = 01b).
0b = Stop channel sequencing.
1b = Start channel sequencing in ascending order for channels enabled in AUTO_SEQ_CH_SEL register.
3-2 RESERVED R 0b Reserved Bit
1-0 SEQ_MODE[1:0] R/W 0b Selects the mode of scanning of analog input channels.
0b = Manual sequence mode; channel selected by MANUAL_CHID field.
1b = Auto sequence mode; channel selected by AUTO_SEQ_CHSEL.
10b = On-the-fly sequence mode.
11b = Reserved.

7.5.12 CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]

CHANNEL_SEL is shown in Figure 7-27 and described in Table 7-22.

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Figure 7-27 CHANNEL_SEL Register
7 6 5 4 3 2 1 0
RESERVED MANUAL_CHID[3:0]
R-0b R/W-0b
Table 7-22 CHANNEL_SEL Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0b Reserved Bit
3-0 MANUAL_CHID[3:0] R/W 0b In manual mode (SEQ_MODE = 00b), this field contains the 4-bit channel ID of the analog input channel for next ADC conversion. For valid ADC data, the selected channel must not be configured as GPIO in PIN_CFG register. 1xxx = Reserved.
0b = AIN0
1b = AIN1
10b = AIN2
11b = AIN3
100b = AIN4
101b = AIN5
110b = AIN6
111b = AIN7
1000b = Reserved.

7.5.13 AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]

AUTO_SEQ_CH_SEL is shown in Figure 7-28 and described in Table 7-23.

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Figure 7-28 AUTO_SEQ_CH_SEL Register
7 6 5 4 3 2 1 0
AUTO_SEQ_CH_SEL[7:0]
R/W-0b
Table 7-23 AUTO_SEQ_CH_SEL Register Field Descriptions
Bit Field Type Reset Description
7-0 AUTO_SEQ_CH_SEL[7:0] R/W 0b Select analog input channels AIN[7:0] in for auto sequencing mode.
0b = Analog input channel is not enabled in scanning sequence.
1b = Analog input channel is enabled in scanning sequence.

7.5.14 DIAGNOSTICS_KEY Register (Address = 0xBF) [reset = 0x0]

DIAGNOSTICS_KEY is shown in Figure 7-29 and described in Table 7-24.

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Figure 7-29 DIAGNOSTICS_KEY Register
7 6 5 4 3 2 1 0
DIAG_KEY[7:0]
R/W-0b
Table 7-24 DIAGNOSTICS_KEY Register Field Descriptions
Bit Field Type Reset Description
7-0 DIAG_KEY[7:0] R/W 0b Enable write access to diagnostics registers in address locations 0xC0, 0xC1, and 0xC2. Write 0x96 to this register to enable write access to diagnostics registers.

7.5.15 DIAGNOSTICS_EN Register (Address = 0xC0) [reset = 0x0]

DIAGNOSTICS_EN is shown in Figure 7-30 and described in Table 7-25.

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Figure 7-30 DIAGNOSTICS_EN Register
7 6 5 4 3 2 1 0
RESERVED VTEST_EN RESERVED BITWALK_EN
R-0b R/W-0b R-0b R/W-0b
Table 7-25 DIAGNOSTICS_EN Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 0b Reserved Bit
4 VTEST_EN R/W 0b Enable measurement of internal 1.8 V (typical) test voltage using AIN6. When using this mode, AIN6 pin should not be left floating and should not be connected to any external circuit. If BITWALK_EN = 1b, this bit has no effect.
0b = Normal operation.
1b = AIN6 is internally connected to 1.8V (typical) test voltage. AIN6 pin should be floating and should not be connected to any external circuit.
3-1 RESERVED R 0b Reserved Bit
0 BITWALK_EN R/W 0b Enable bit-walk mode of the ADC bit decisions.
0b = Normal operation.
1b = Bit walk mode enabled.

7.5.16 BIT_SAMPLE_LSB Register (Address = 0xC1) [reset = 0x0]

BIT_SAMPLE_LSB is shown in Figure 7-31 and described in Table 7-26.

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Figure 7-31 BIT_SAMPLE_LSB Register
7 6 5 4 3 2 1 0
BIT_SAMPLE_LSB[7:0]
R/W-0b
Table 7-26 BIT_SAMPLE_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 BIT_SAMPLE_LSB[7:0] R/W 0b Define the [7:0] bit positions during sampling phase of the ADC. This field has no effet when DIAG_EN = 0.

7.5.17 BIT_SAMPLE_MSB Register (Address = 0xC2) [reset = 0x0]

BIT_SAMPLE_MSB is shown in Figure 7-32 and described in Table 7-27.

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Figure 7-32 BIT_SAMPLE_MSB Register
7 6 5 4 3 2 1 0
BIT_SAMPLE_MSB[7:0]
R/W-0b
Table 7-27 BIT_SAMPLE_MSB Register Field Descriptions
Bit Field Type Reset Description
7-0 BIT_SAMPLE_MSB[7:0] R/W 0b Define the [15:8] bit positions during sampling phase of the ADC. This field has no effet when DIAG_EN = 0.