ZHCSLR7A March   2021  – October 2021 ADS7067

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
      2. 7.3.2  Reference
        1. 7.3.2.1 External Reference
        2. 7.3.2.2 Internal Reference
      3. 7.3.3  ADC Transfer Function
      4. 7.3.4  ADC Offset Calibration
      5. 7.3.5  Programmable Averaging Filters
      6. 7.3.6  CRC on Data Interface
      7. 7.3.7  Oscillator and Timing Control
      8. 7.3.8  Diagnostic Modes
        1. 7.3.8.1 Bit-Walk Test Mode
        2. 7.3.8.2 Fixed Voltage Test Mode
      9. 7.3.9  Output Data Format
        1. 7.3.9.1 Status Flags
        2. 7.3.9.2 Output CRC (Device to Host)
        3. 7.3.9.3 Input CRC (Host to Device)
      10. 7.3.10 Device Programming
        1. 7.3.10.1 Enhanced-SPI Interface
        2. 7.3.10.2 Daisy-Chain Mode
        3. 7.3.10.3 Register Read/Write Operation
          1. 7.3.10.3.1 Register Write
          2. 7.3.10.3.2 Register Read
            1. 7.3.10.3.2.1 Register Read With CRC
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power-Up and Reset
      2. 7.4.2 Manual Mode
      3. 7.4.3 On-the-Fly Mode
      4. 7.4.4 Auto-Sequence Mode
    5. 7.5 ADS7067 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Charge-Kickback Filter and ADC Amplifier
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 AVDD and DVDD Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.9.3 Input CRC (Host to Device)

When the CRC module is enabled, the host must always communicate with the ADC using 32-bit SPI frames comprised of a 24-bit data payload and an 8-bit CRC byte. The host must calculate the CRC byte to be appended based on a 24-bit payload. The ADC computes a CRC over the 24-bit data payload and compares the result with the CRC received from the host.Table 7-4 lists the output data frames for the CRC_EN bit.

Table 7-4 Output Data Frames
CRC_EN OSR[2:0] APPEND_STATUS[1:0] OUTPUT DATA FRAME
CRC module disabled
(CRC_EN = 0)		 No averaging No flags (00b or 11b) {Conversion result [15:0], 8'b0}
Channel ID (01b) {Conversion result [15:0], CHID[3:0], 4'b0}
Status flags (10b) {Conversion result [15:0], status flags[3:0], 4'b0}
Averaging enabled No flags (00b or 11b) {Conversion result [19:0], 4'b0}
Channel ID (01b) {Conversion result [19:0], CHID[3:0]}
Status flags (10b) {Conversion result [19:0], status flags[3:0]}
CRC module enabled
(CRC_EN = 1)		 No averaging No flags (00b or 11b) {Conversion result [15:0], CRC[7:0], 8'b0}
Channel ID (01b) {Conversion result [15:0], CHID[3:0], 4'b0, CRC[7:0]}
Status flags (10b) {Conversion result [15:0], status flags[3:0], 4'b0, CRC[7:0]}
Averaging enabled No flags (00b or 11b) {Conversion result [19:0], 4'b0, CRC[7:0]}
Channel ID (01b) {Conversion result [19:0], CHID[3:0], CRC[7:0]}
Status flags (10b) {Conversion result [19:0], status flags[3:0], CRC[7:0]}