ZHCSPO3 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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6.9 Timing Requirements

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC TIMING SPECIFICATIONS
TAD Aperture Delay 0.17 ns
Aperure Delay variation 0.07
TA Aperture Jitter 50 fs
Overload recovery time 3-dB overload condition 10 clock cycles
6-dB overload condition 50
tADC ADC latency from sampling instant to internal hand-off to digital 68 ADC clock cycles
Internal propagation delay 5 ns
Latency adder for 2x averaging 4 ADC clock cycles
Deterministic delay from digital block (DDC (if used) and JESD interface) LMFS = 8-4-8-10 163 ADC clock cycles
LMFS = 8-4-2-2 131
4x real decimation, LMFS = 8-4-2-2 456
4x decimation, F (number of octets) = 2 394
4x decimation, F = 4 374
4x decimation, F = 8 367
8x decimation, F = 2 560
8x decimation, F = 4 520
8x decimation, F = 8 506
8x decimation, F = 16 491
16x decimation, F = 2 900
16x decimation, F = 4 820
16x decimation, F = 8 792
16x decimation, F = 16 762
16x decimation, F = 32 748
32x decimation, F = 2 1596
32x decimation, F = 4 1436
32x decimation, F = 8 1380
32x decimation, F = 16 1320
32x decimation, F = 32 1292
64x decimation, F = 2 2940
64x decimation, F = 4 2620
64x decimation, F = 8 2508
64x decimation, F = 16 2388
64x decimation, F = 32 2332
128x decimation, F = 2 5668
128x decimation, F = 4 5028
128x decimation, F = 8 4804
128x decimation, F = 16 4564
128x decimation, F = 32 4452
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency 1 20 MHz
tSU(SEN) SEN to rising edge of SCLK 10 ns
tH(SEN) SEN from rising edge of SCLK 10 ns
tSU(SDIO) SDIO to rising edge of SCLK 10 ns
tH(SDIO) SDIO from rising edge of SCLK 10 ns
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t(OZD) SDIO tri-state to driven 10 ns
t(ODZ) SDIO data to tri-state 14 ns
t(OD) SDIO valid from falling edge of SCLK 10 ns
TIMING: SYSREFP/M
ts(SYSREF) Setup time, SYSREFP/M valid to rising edge of CLKP/M 50 ps
th(SYSREF) Hold time, SYSREFP/M valid to rising edge of CLKP/M 50 ps
CML SERDES OUTPUTS: DOUT[0..7]P/M
fSerdes Serdes bit rate 0.5 12.8 13.0 Gbps
RJ Random jitter, RMS RPAT, 6.4 Gbps 0.7 ps
RJ Random jitter, RMS RPAT, 12.8 Gbps 0.6 ps
DJ Deterministic jitter, peak to peak RPAT, 6.4 Gbps 8.9 ps
DJ Deterministic jitter, peak to peak RPAT, 12.8 Gbps 14.7 ps
TJ Total jitter, peak to peak RPAT, 6.4 Gbps 19.5 ps
TJ Total jitter, peak to peak RPAT, 12.8 Gbps 24