ZHCSPO3 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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7.3.5 Decimation Filter

The ADC34RF52 provides up to two digital down converters per ADC channel (see Figure 7-20). The decimation filters provide a flexible option to cover a wide range of instantaneous bandwidths (IBW) as shown in Table 7-15. Single band decimation supports a wide bandwidth up to complex decimation by 4x. In dual band decimation mode the widest bandwidth supported is complex decimation by 8.

GUID-3BE1A131-C1D0-4011-B875-C08BF0AEDA63-low.gifFigure 7-20 Digital Decimation Filter Options
Table 7-15 Summary of Different Decimation Filter Band Options
# of DDCsMinimum Complex DecimationMaximum Complex Decimation
14128
28128

The decimation filter can be configured to two different operating modes:

  • Complex Decimation: This mode provides complex output with ~ 80% passband bandwidth using a 48-bit phase coherent NCO.
    During the complex mixing operation the digital output is reduced by 6-dB. This reduces the fullscale from 0-dBFS to -6-dBFS. This 6-dB change applies to signals and noise and thus no dynamic range is lost.
  • Real Decimation: In real decimation mode the complex mixer is bypassed (NCO should be set to 0 for lowest power consumption) and the digital filter acts as a low pass filter. There is no frequency shifting and the output passband bandwidth is ~ 40%.

Since the JESD204B interface is common across all ADC channels, the decimation ratio as well as the # of DDCs/ADC has to be the same across all ADC channels.

By default, the output of values of the decimation filter are rounded to 16-bit resolution. To avoid quantization noise limitation when using high order of decimation (that is, /64 or /128), a special 32-bit output mode can be enabled (see 32-bit mode).

Table 7-16 provides an overview of the available complex decimation settings and resulting complex and real output bandwidths.

Table 7-16 Decimation Setting vs Output Bandwidth
Decimation Factor N (complex)Complex Output Bandwidth per DDCFS = 1.5 GspsReal Output Bandwidth per DDCFS = 1.5 Gsps
Complex Output Rate per DDCComplex Output Bandwidth per DDCReal Output Rate per DDCReal Output Bandwidth per DDC
4 0.8 x FS / 4 375 Msps 300 MHz 0.4 x FS / 4 375 Msps 150 MHz
8 0.8 x FS / 8 187.5 Msps 150 MHz 0.4 x FS / 8 187.5 Msps 75 MHz
160.8 x FS / 1693.75 Msps75 MHz0.4 x FS / 1693.75 Msps37.5 MHz
320.8 x FS / 3246.875 Msps37.5 MHz0.4 x FS / 3246.875 Msps18.75 MHz
640.8 x FS / 6423.4375 Msps18.75 MHz0.4 x FS / 6423.4375 Msps9.375 MHz
1280.8 x FS / 12811.71875 Msps9.375 MHz0.4 x FS / 12811.71875 Msps4.6875 MHz