ZHCSPO3 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band

Table 7-35 lists the available JESD204B interface formats and corresponding valid sampling rate ranges for the ADC34RF52 with complex decimation (dual band). The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes are shown in Table 7-39, Table 7-37 and Table 7-38.

Table 7-35 JESD Mode Options: Decimation - Dual Band
DECIMATION
SETTING D
(complex)		LMFSMIN FS
(Gsps)		MAX FS
(Gsps)		RATIO
[fSERDES/(FS/D)]
/8 8 16 4 1 0.5 1.5 40
/16
/32
/640.8
/8 4 16 8 1 0.5 1.5 80
/16
/32
/64
/1280.8
/82161610.50.65160
/16 1.3
/32 1.5
/64
/128
/161163210.50.65320
/321.3
/64 1.5
/128
Table 7-36 JESD Sample Frame Assembly: Decimation - Dual Band
OUTPUT
LANE		LMFS = 8-16-4-1LMFS = 4-16-8-1
DOUT0A1I0
[15:8]		A1I0
[7:0]		A1Q0
[15:8]		A1Q0
[7:0]		A1I0
[15:8]		A1I0
[7:0]		A1Q0
[15:8]		A1Q0
[7:0]		A2I0
[15:8]		A2I0
[7:0]		A2Q0
[15:8]		A2Q0
[7:0]
DOUT1A2I0
[15:8]		A2I0
[7:0]		A2Q0
[15:8]		A2Q0
[7:0]		B1I0
[15:8]		B1I0
[7:0]		B1Q0
[15:8]		B1Q0
[7:0]		B2I0
[15:8]		B2I0
[7:0]		B2Q0
[15:8]		B2Q0
[7:0]
DOUT2B1I0
[15:8]		B1I0
[7:0]		B1Q0
[15:8]		B1Q0
[7:0]		C1I0
[15:8]		C1I0
[7:0]		C1Q0
[15:8]		C1Q0
[7:0]		C2I0
[15:8]		C2I0
[7:0]		C2Q0
[15:8]		C2Q0
[7:0]
DOUT3B2I0
[15:8]		B2I0
[7:0]		B2Q0
[15:8]		B2Q0
[7:0]		D1I0
[15:8]		D1I0
[7:0]		D1Q0
[15:8]		D1Q0
[7:0]		D2I0
[15:8]		D2I0
[7:0]		D2Q0
[15:8]		D2Q0
[7:0]
DOUT4CI0
[15:8]		C1I0
[7:0]		C1Q0
[15:8]		C1Q0
[7:0]
DOUT5C2I0
[15:8]		C2I0
[7:0]		C2Q0
[15:8]		C2Q0
[7:0]
DOUT6D1I0
[15:8]		D1I0
[7:0]		D1Q0
[15:8]		D1Q0
[7:0]
DOUT7D2I0
[15:8]		D2I0
[7:0]		D2Q0
[15:8]		D2Q0
[7:0]
Table 7-37 JESD Sample Frame Assembly: Decimation - Dual Band
OUTPUT
LANE		LMFS = 2-16-16-1
DOUT0A1I0
[15:8]		A1I0
[7:0]		A1Q0
[15:8]		A1Q0
[7:0]		A2I0
[15:8]		A2I0
[7:0]		A2Q0
[15:8]		A2Q0
[7:0]		B1I0
[15:8]		B1I0
[7:0]		B1Q0
[15:8]		B1Q0
[7:0]		B2I0
[15:8]		B2I0
[7:0]		B2Q0
[15:8]		B2Q0
[7:0]
DOUT1C1I0
[15:8]		C1I0
[7:0]		C1Q0
[15:8]		C1Q0
[7:0]		C2I0
[15:8]		C2I0
[7:0]		C2Q0
[15:8]		C2Q0
[7:0]		D1I0
[15:8]		D1I0
[7:0]		D1Q0
[15:8]		D1Q0
[7:0]		D2I0
[15:8]		D2I0
[7:0]		D2Q0
[15:8]		D2Q0
[7:0]
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
Table 7-38 JESD Sample Frame Assembly: Decimation - Dual Band
OUTPUT
LANE		LMFS = 1-16-32-1
DOUT0A1I0
[15:8]		A1I0
[7:0]		A1Q0
[15:8]		A1Q0
[7:0]		A2I0
[15:8]		A2I0
[7:0]		A2Q0
[15:8]		A2Q0
[7:0]		B1I0
[15:8]		B1I0
[7:0]		B1Q0
[15:8]		B1Q0
[7:0]		B2I0
[15:8]		B2I0
[7:0]		B2Q0
[15:8]		B2Q0
[7:0]		...
...C1I0
[15:8]		C1I0
[7:0]		C1Q0
[15:8]		C1Q0
[7:0]		C2I0
[15:8]		C2I0
[7:0]		C2Q0
[15:8]		C2Q0
[7:0]		D1I0
[15:8]		D1I0
[7:0]		D1Q0
[15:8]		D1Q0
[7:0]		D2I0
[15:8]		D2I0
[7:0]		D2Q0
[15:8]		D2Q0
[7:0]
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7