ZHCSPO3 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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8.3.1.6 STEP 6: Analog Trim Settings

The following registers must be set for best analog performance. The register write order is all writes in first 2 columns before moving to the next set of address/data in middle columns and so on.

Table 8-9 Analog Trim Setting Registers
ADDR DATA ADDR DATA COMMENT ADDR DATA COMMENT
0x05 0x40 0x3B 0x0C 0x56 0x03
0xE8 0xF0 0xA8 0x18 Only for 1x AVG 0x56 0x07
0xE9 0x01 0xA8 0x00 Only for 2x AVG, FS<1.1 GSPS 0x56 0x0F
0x4B 0x1F 0xA8 0x08 Only for 2x AVG, FS=1.1-1.5 GSPS 0x6E 0x08
0x5B 0x01 0xCD 0x00 0x102 0x02
0xEA 0x00 0xCE 0x00 0x103 0xD9
0xEB 0x03 0x100 See Table 8-10for sample rate dependent trim registers 0xA7 0x00
0x95 0x00 0x101 0xA6 0x08
0xFC 0x28 0x104 0x05 0x20
0xE0 0x8E 0x105 0xC9 0x09
0xE1 0x03 0x107 0x10 0x102 0xFE
0x4C 0x40 0x05 0x20 0x103 0x03
0x4E 0x01 0x30 0xE8 0x104 0xD4
0x4E 0x00 0x31 0xFF 0x105 0x03
0xA1 0x01 0x30 0x08 0x106 0xFE
0xF8 0x00 0x31 0x80 0x107 0x03
0x31 0x20 0x32 0x03 0x108 0xBC
0xFD 0x1C 0x05 0x02 0x109 0x1A
0xAA 0x02 0x243 0x02 0x101 0x01
0x4D 0x80 0x05 0x20 0x159 0x63
0xB3 0x30 0x36 0x04 0x05 0x40
0x64 0x10 0x1F8 0x01 0x31 0x00
0x62 0x12 0x1FC 0x0A 0x4D 0x00
0xFE 0x80 0x1F0 0x20 0x62 0x10
0xFC 0x28 0x1F1 0x0C 0x56 0x0E
0xFF 0x14 0x05 0x40 0x56 0x0C
0x106 0x00 0x39 0x40 0x56 0x08
0x107 0x00 0x56 0x01 0x56 0x00
0x6E 0x00
0xF8 0x06
Table 8-10 Sample rate dependent trim registers
FS (GSPS) 0x100 0x101 0x104 0x105
0.6-0.7 0x48 0x00 0x01 0x01
0.7-0.9 0xC8 0x01 0x81 0x00
0.9-1.1 0x48 0x01 0x81 0x00
1.1-1.3 0xC8 0x00 0x81 0x00
1.3-1.5 0x48 0x00 0x81 0x00