ZHCSPO3 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

5 Pin Configuration and Functions

GUID-20230217-CA0I-ZCLK-GRR5-5S5RTZF85DBR-low.svgFigure 5-1 RTD Package, 64 Pin QFN (Top View)
Table 5-1 Pin Functions
PINTYPEDESCRIPTION
NAMENO.
ANALOG INPUTS
INAP14IDifferential analog input for channel A. 100 Ω differential internal termination.
INAM15
INBP18IDifferential analog input for channel B. 100 Ω differential internal termination.
INBM19
INCP35IDifferential analog input for channel C. 100 Ω differential internal termination.
INCM34
INDP31IDifferential analog input for channel D. 100 Ω differential internal termination.
INDM30
VCM26OCommon-mode voltage output for the analog inputs.
CLOCK, SYNCHRONIZATION
CLKP23IDifferential sampling clock input. 100 Ω differential internal termination.
CLKM24
SYSREFP27IDifferential external synchronization input.
SYSREFM28
CONTROL
RESETb11IHardware reset. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD18.
SEN57ISerial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD18.
SCLK55ISerial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO56I/OSerial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
GPIO139I/OGPIO control pin. This pin is configured through SPI interface for power down or NCO control function.
GPIO238I/OGPIO control pin. This pin is configured through SPI interface for power down or NCO control function.
SPISEL10IDetermines the functional of the SPI interface pins: either normal SPI for register programming or fast access to NCO selection only for fast frequency hopping.
DIGITAL DATA INTERFACE
DOUT0P4OJESD204B high-speed serial data output interface pins for channels A to D. Output lanes can be reordered using the output MUX.
DOUT0M5
DOUT1P1O
DOUT1M2
DOUT2P63O
DOUT2M64
DOUT3P60O
DOUT3M61
DOUT4P45O
DOUT4M44
DOUT5P48O
DOUT5M47
DOUT6P50O
DOUT6M49
DOUT7P53O
DOUT7M52
POWER SUPPLY
AVDD1817,20,29,32, 58IAnalog 1.8-V power supply
AVDD1213,16,21,33, 36IAnalog 1.2-V power supply
CLKVDD25IClock 1.2-V power supply. Very sensitive to power supply noise. Directly impacts close in aperture phase noise.
DVDD3,7,9,40,42, 46,54,59IDigital 1.2-V power supply
AGND12,37IAnalog ground, shorted to thermal pad.
CLKGND22IClock ground.
DGND6,8,41,43,51,62IDigital ground.