ZHCSPO3 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6 Register Maps

Table 7-46 Register Map Summary
PAGE REGISTER
ADDRESS		 REGISTER DATA
A[11:0] D7 D6 D5 D4 D3 D2 D1 D0
GLOBAL 0x00 0 0 0 0 0 0 0 RESET
0x05 0 ANALOG PAGE CALIB PAGE DDCCD PAGE DDCAB PAGE JESD PAGE DIGITAL PAGE 0
DIGITAL 0x2C 20-BIT OUT DDC BAND SEL 0 0 0 DDC REAL BYP EN
0x2D 0 DECIMATION 0 0 0 0
0x2E 0 0 0 0 AVG EN AVG SEL(1) 0
0x33 0 0 0 1 FORMAT 0 GBL PDN 0
0x34 0 MEM STROBE MEM CH SEL 0 0 0 0
0x3B NCO2 CHB [1:0] NCO1 CHB [1:0] NCO2 CHA [1:0] NCO1 CHA [1:0]
0x41 NCO2 CHD [1:0] NCO1 CHD [1:0] NCO2 CHC [1:0] NCO1 CHC [1:0]
0x22F 1 SYSREF X5 SYSREF X4 SYSREF X3 SYSREF X2 SYSREF X1 SYSREF OR 1
0x234 0 NCO SEL MODE 0 0 GPIO MODE
0X235 NCO SEL SOURCE
0x236 0 GPIO2 INV GPIO1 INV GPIO SWAP 0 0 SYSREF RESET SYSREF EN
0x238 OVR OUTPUT CFG 0 0 0 0
JESD 0x20 K
0x21 0 SYNC SPI EN SYNC SPI 0 0 SYSREF MODE
0x22 LMFS MODE
0x24 DDC CLK DIV
0x25 JESD TX CLK DIV
0x27 0 0 DROP LSB 0 0 0 CLK BAL EN 0
0x28 JESD TX LANE EN
0x2B 0 0 0 0 0 0 0 SYNC INV
0x2D 0 0 0 0 0 TEST SEQ SEL
0x2E RAMP INCR 0 RAMP EN ALT PAT 0
0x2F 0 PRBS PAT PRBS EN 0 JESD PRBS PAT JESD PRBS EN
0x30 START VALUE JESD RAMP DOUT0
0x32 START VALUE JESD RAMP DOUT1
0x34 START VALUE JESD RAMP DOUT2
0x36 START VALUE JESD RAMP DOUT3
0x40 START VALUE JESD RAMP DOUT4
0x42 START VALUE JESD RAMP DOUT5
0x44 START VALUE JESD RAMP DOUT6
0x46 START VALUE JESD RAMP DOUT7
0x53 SCR EN 0 0 0 0 0 0 0
0x5C F in ILA
0x5D K in ILA
JESD 0x7A JESD LANE POL INV
0x80 0 LANE DOUT1 SEL 0 LANE DOUT0 SEL
0x81 0 LANE DOUT3 SEL 0 LANE DOUT2 SEL
0x82 0 LANE DOUT5 SEL 0 LANE DOUT4 SEL
0x83 0 LANE DOUT7 SEL 0 LANE DOUT6 SEL
0x84 0 0 0 0 0 0 JESD PLL FACTOR
0x89 TX EMPH DOUT1 [0] TX EMPH DOUT0 [5:0] 0
0x8A 0 0 0 TX EMPH DOUT1 [5:1]
0x8B TX EMPH DOUT3 [0] TX EMPH DOUT2 [5:0] 0
0x8C 0 0 0 TX EMPH DOUT3 [5:1]
0x8D TX EMPH DOUT5 [0] TX EMPH DOUT4 [5:0] 0
0x8E 0 0 0 TX EMPH DOUT5 [5:1]
0x8F TX EMPH DOUT7 [0] TX EMPH DOUT6 [5:0] 0
0x90 0 0 0 TX EMPH DOUT7 [5:1]
0x9D PD DOUT7 [0] PD DOUT6 [0] PD DOUT5 [0] PD DOUT4 [0] PD DOUT3 [0] PD DOUT2 [0] PD DOUT1 [0] PD DOUT0 [0]
0x9E PD DOUT7 [1] PD DOUT6 [1] PD DOUT5 [1] PD DOUT4 [1] PD DOUT3 [1] PD DOUT2 [1] PD DOUT1 [1] PD DOUT0 [1]
0x9F 0 JESD PLL1 0 JESD PLL2
0xA0 0 JESD PLL INPUT1 0 0 0 0
0xA1 0 JESD PLL INPUT2 0 0 0 0
0xA2 0 0 0 0 JESD PLL INPUT3 0
0xED 0 0 JESD DDC BYP 0 0 0 0
DDCAB/CD 0x100..0x105 NCO1 CHA/C FREQUENCY1 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x108..0x10D NCO1 CHA/C FREQUENCY2 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x110..0x115 NCO1 CHA/C FREQUENCY3 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x118..0x11D NCO1 CHA/C FREQUENCY4 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x120..0x125 NCO2 CHA/C FREQUENCY1 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x128..0x12D NCO2 CHA/C FREQUENCY2 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x130..0x135 NCO2 CHA/C FREQUENCY3 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x138..0x13D NCO2 CHA/C FREQUENCY4 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x140..0x145 NCO1 CHB/D FREQUENCY1 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x148..0x14D NCO1 CHB/DFREQUENCY2 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x150..0x155 NCO1 CHB/DFREQUENCY3 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x158..0x15D NCO1 CHB/DFREQUENCY4 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x160..0x165 NCO2 CHB/DFREQUENCY1 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x168..0x16D NCO2 CHB/DFREQUENCY2 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x170..0x175 NCO2 CHB/DFREQUENCY3 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x178..0x17D NCO2 CHB/DFREQUENCY4 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
0x181 0 0 LOAD NCO 0 0 0 0
CALIBRATION 0x34 0 0 0 0 0 AVG SEL(2) 1
0x45 CAL SPI CAL GPIO 0 0 1 0 1 0
0x298 0 0 0 0 CAL STATUS
ANALOG 0x7B 0 0 TERM AB 0 0 0 0 TERM AB
0x8B 0 0 TERM CD 0 0 0 0 TERM CD
0xA8 0 DITHER AMP1 0 0 0
0xAF DITHER DIS 0 0 1 0 0 0 0
0xB1 DITHER DIVIDER
0xB4 0 0 0 0 0 0 0 SYSREF AC EN
0xCD 0 DITH AMP2 0 0 0 0
0xE6 TX SWING [0] 0 0 0 0 0 0 0
0xE7 0 0 0 0 0 0 TX SWING [2:1]