ZHCSPO3 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.1.9 STEP 9: Run Power up Calibration

The following registers start the power up foreground calibration. The register write order is all writes in first 2 columns before moving to the next set of address/data in middle columns and so on.

Table 8-13 Calibration Register Settings
ADDRESS DATA ADDRESS DATA ADDRESS DATA
0x05 0x20 0x93 0x20 0x58 0x30
0xE7 0x01 0x20 0x00 0x58 0x20
0x174 0x02 0x05 0x00 0x58 0x00
0x178 0x00 0x04 0x01 0x89 x020
0x17C 0x22 0x20 0x1F 0x95 0x00
0x3C 0x00 0x93 0x20 0x96 0x00
0xFC 0x03 0x04 0x01 0x97 0x10
0xFD 0x00 0x20 0x00 0x9C 0x00
0x154 0x1C 0x04 0x00 0x57 0x1E
0x155 0x03 0x05 0x20 0x46 0x02
0xFC 0x03 0xC0 0x7C 0x45 0x8A
0xEE 0x26 0xBC 0x3C 0x45 0x0A
0xEF 0x02 0xC9 0x01 Delay 3 seconds
0x18C 0x88 0xC9 0x00 0x89 0x00
0xAE 0xC8 0xC9 0x06 0x95 0x00
0xAF 0x00 0x38 0x01 0x96 0x00
0xB0 0x4C 0x110 0x10 0x97 0x00
0xB1 0x3F 0x111 0x42 0x9C 0x00
0x4F 0x46 0x112 0xA6 0x57 0x1A
0x50 0x2C 0x112 0xD6 0x57 0x3A
0x51 0x05 0x113 0xBB 0x57 0x7A
0x154 0x7C 0x113 0xDB 0x57 0xFA
0x158 0x7C 0x114 0xF4 0x58 0x01
0x159 0x6F 0x114 0x64 0x58 0x03
0x15C 0x7C 0x115 0x0E 0x58 0x07
0x15D 0x3F 0x115 0xFE 0x58 0x0F
0x160 0x7C 0x116 0x0D 0x58 0x1F
0x161 0x3F 0x116 0xDD 0x58 0x3F
0x164 0x7C 0x117 0x0D 0x45 0x8A
0x165 0x4F 0x117 0xDD 0x45 0x0A
0x16C 0x7C 0x46 0x03 Delay 3 seconds
0x1B0 0x1C 0x3D 0x00 0x47 0xC0
0x1B1 0x5F 0x45 0x0A 0x46 0x03
0x1D8 0x1C 0x46 0x02 0x47 0xC0
0x1D9 0xAF 0x64 0x4A 0x05 0x80
0xB2 0x1F 0x65 0x05 0x20 0x1F
0xB5 0x7F 0x68 0x28 0x9D 0x05
0x165 0xFF 0x69 0x5E 0x9E 0x08
0x38 0x01 0x6A 03D 0x8B 0x40
0xA4 0x30 0x6B 0x8F 0x20 0x00
0xC5 0x7F 0x6C 0x44 0x05 0x00
0xA8 0x00 0x57 0xDA 0x04 0x01
0xA2 0x63 0x57 0x9A 0x20 0x1F
0xA3 0x00 0x57 0x1A 0x9D 0x05
0xAD 0x02 0x58 0x3E 0x9E 0x08
0x05 0x80 0x58 0x3C 0x8B 0x40
0x20 0x1F 0x58 0x38