SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.3.4.1 SYSREF Monitor

The SYSREF monitor compares the incoming SYSREF signal to the ADC sampling clock by latching the incoming SYSREF signal with copies of the sampling clock that have an analog delay. The latched outputs are processed internally through the SYSREF processing block and the final output is provided to the user. The latched flop outputs are used to check if there exists enough margin between the CLK and SYSREF rising edges (set up and hold times). If a set up and hold violation is detected, a programmable delay td can be used to adjust the SYSREF delay such that there is adequate margin between CLK and SYSREF for SYSREF to be latched properly.

ADC32RF72 SYSREF Detection CircuitryFigure 7-10 SYSREF Detection Circuitry

The following parameters can be programmed:

Table 7-7 SYSREF Configuration Programming

System Parameter

Name		SizeDefaultAccessDescription
SYSREF_MONITOR_NUM_POLLS81R/WSets the number of SYSREF rising edges to be detected before SYSREF_MONITOR_OUT is updated. Higher values of SYSREF_MONITOR_NUM_POLLS can be used to gauge the SYSREF edge spread since each flop output is ORed with all of the previous outputs until SYSREF_MONITOR_NUM_POLLS SYSREF rising edges are seen.
1...255: Number of SYSREF rising edges to be seen before SYSREF_MONITOR_OUT is updated.
SYSREF_MONITOR_TD_COARSE40R/WSets the number of coarse delays (45ps) in the td block.
SYSREF_MONITOR_TD_FINE40R/WSets the fine delay in the td block.
td_fine = (floor(SYSREF_MONITOR_TD_FINE/2)*15ps) + ((SYSREF_MONITOR_TD_FINE%2)*4ps)
SYSREF_MONITOR_OUT80RSYSREF monitor output. Bit 0 corresponds to the earliest CLK edge and bit 7 corresponds to the latest CLK edge.
The SYSREF_MONITOR_OUT can only be in one of the following states and can be interpreted as follows:
State 0: One or more zeros followed by one or more ones. A rising of SYSREF transition is in the SYSREF monitor window and set up and hold violation is detected. SYSREF_LAT must be delayed until all zeros or all ones are observed.
State 1: all zeros. CLK is leading SYSREF_LAT and SYSREF_LAT is latched properly by the next CLK rising edge.
State 2: all ones CLK is lagging SYSREF_LAT and SYSREF_LAT is latched properly by the current CLK rising edge.