SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.3.5.5.1 Decimation Filter Input

There are several different multiplexers available at the input of each of the 8x DDC as shown in Figure 7-22. Each DDC has a DDC_REAL_DATA_MUX and DDC_INPUT_DATA_TYPE_MUX. The DDC input data type is based on the ddc_mode setting.

ADC32RF72 DDC Input Data Muxing Figure 7-22 DDC Input Data Muxing

The following parameters can be programmed:

Table 7-13 Input Selection to the DDC Programming

System Parameter Name

SizeDefaultAccessDescription
DDC_AVG__SEL{0,2}3..R/W

Select the two data streams to be averaged in the 2x AVG as a shared input for the multiplexers DDC_REAL_DATA_MUX[3:0]/[7:4].

0: Average of dsp_out[0] and dsp_out[1].

1: Average of dsp_out[0] and dsp_out[2].

2: Average of dsp_out[0] and dsp_out[3].

3: Average of dsp_out[1] and dsp_out[2].

4: Average of dsp_out[1] and dsp_out[3].

5: Average of dsp_out[2] and dsp_out[3].

DDC_IN_SRC_SEL{0..7}5..R/W

Select the data source for DDC{0..7}. All DDC data must come exclusively from only one of the multiplexers.

0: dsp_out[0] as real input to the DDC.

1: dsp_out[1] as real input to the DDC.

2: dsp_out[2] as real input to the DDC.

3: dsp_out[3] as real input to the DDC.

4: Output of the first 2x AVG block (DDC_AVG_SEL_0/2) block as real input to the DDC.

5: Output of the second 2x AVG block (DDC_AVG_SEL_1/3) block as real input to the DDC.

6: Average of dsp_out[0], dsp_out[1], dsp_out[2], and dsp_out[3] as real input to the DDC.

DDC_EN_CTRL80R/W

Individual DDC enable control. Each bit corresponds to one DDC where the LSB corresponds to DDC0. If the enable bit is set then the corresponding DDC is enabled.

Bit 0: DDC0 power down control.

Bit 1: DDC1 power down control.

Bit 2: DDC2 power down control.

Bit 3: DDC3 power down control.

Bit 4: DDC4 power down control.

Bit 5: DDC5 power down control.

Bit 6: DDC6 power down control.

Bit 7: DDC7 power down control.

DDC_MODE_SEL30R/W

Select the DDC mode which is shared across all DDCs.

0: Pass-through mode; The particular DDC is unused

1: Real input (from the DDC_REAL_DATA_MUX) given to the DDCs is low pass filtered and down sampled by the decimation factor.

2: Real input (from the DDC_REAL_DATA_MUX) given to the DDCs is mixed with an NCO to produce a complex output. The complex output is low pass filtered and down sampled by the decimation factor.