SBASAL2 November   2025 ADC32RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 ADC Channel Selection and Power Down Modes
      3. 7.3.3 Sampling Clock Input
      4. 7.3.4 SYSREF
        1. 7.3.4.1 SYSREF Monitor
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly With Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.3.5.1 DSP Input Mux

There are 4 digital multiplexers at the input of the DSP blocks as shown in Figure 7-12. The bus is referred to adc_out[3:0] where each index refers to the unique output stream of a particular ADC, meaning, the ADC0 output is adc_out[0] and so on. The output of each DSP_IN mux corresponds to a single DSP input data stream for the DSP blocks. The aggregate set of DSP input data streams is referred to as dsp_in[3:0]. dsp_in[0] corresponds to the 0th DSP input data stream. Each DSP input data stream can be sourced from one of the following:

  • One of two adc_out streams (adc_out[0] and any one of the others). This is denoted by C(2,1).
  • The average of two adc_out streams.

Note: The nomenclature C(n,k) represents the possible combinations of choosing k items from a set containing n distinct items.
For example, assuming we have a set adc_out={adc0,adc1,adc2,adc3}, there are 6 distinct ways to select two items from the set which can be seen here: C(adc_out,2)={{ADC0,ADC1},{ADC0,ADC2},{ADC0,ADC3},{ADC1,ADC2},{ADC1,ADC3},{ADC2,ADC3}}
ADC32RF72 DSP Input Mux Overview Figure 7-12 DSP Input Mux Overview

The following parameters can be programmed:

Table 7-8 DSP Input Mux Configuration Programming (x = 0,1,2,3)
System Parameter NameSizeDefaultAccessDescription
DSP_IN_SRC_SEL{x}40,1,2,3R/W

Select the input data source for the dsp_in[0..3] input stream to the DSP blocks.

0: ADC0 data.

1: ADC1 data.

2: ADC2 data.

3: ADC3 data.

4: 2x average of ADC0 and ADC1.

5: 2x average of ADC0 and ADC2.

6: 2x average of ADC0 and ADC3.

7: 2x average of ADC1 and ADC2.

8: 2x average of ADC1 and ADC3.

9: 2x average of ADC2 and ADC3.

Others: not used