ZHCSJF0 February 2019 ADC3244E
PRODUCTION DATA.
The device has an internal low-pass filter in the sampling clock path. This low-pass filter helps improve the aperture jitter of the device. However, in applications where input frequencies are < 200 MHz, noise from the aperture jitter does not dominate the overall SNR of the device. In such applications, the wake-up time from a global power-down can be reduced by bypassing the low-pass filter using the DIS CLK FILT register bit (write 80h to register address 70Ah). As shown in Table 5, setting the DIS CLK FILT bit improves the wake-up time from a global power-down from 85 µs to 55 µs.
DIS CLK FILT
REGISTER BIT |
GLOBAL PDN REGISTER BIT | WAKE-UP TIME | ||
---|---|---|---|---|
TYP | MAX | UNIT | ||
0 | 0→1→0 | 85 | 140 | µs |
1 | 0→1→0 | 55 | 81 | µs |