ZHCSJF0 February 2019 ADC3244E
PRODUCTION DATA.
The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 7x sample frequency because seven data bits are output every clock cycle on each differential pair. Each ADC sample is sent over the two wires with the seven MSBs on Dx1P, Dx1M and the seven LSBs on Dx0P, Dx0M, as shown in Figure 49. Note that in two-wire mode, the frame clock (FCLK) frequency is half of sampling clock (CLKIN) frequency.