ZHCSJF0 February 2019 ADC3244E
PRODUCTION DATA.
MIN | TYP | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
tSU | Data setup time: data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM)(5) |
0.36 | 0.42 | ns | |||
tHO | Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid(5) | 0.36 | 0.47 | ns | |||
LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM) | 49% | ||||||
tPDI | Clock propagation delay: input clock falling edge cross-over to frame clock rising edge cross-over 10 MSPS < sampling frequency <
125 MSPS |
1-wire mode | 2.7 | 4.5 | 6.5 | ns | |
2-wire mode | 0.44 × tS + tDELAY | ||||||
tDELAY | Delay time | 3 | 4.5 | 5.9 | ns | ||
tFALL,
tRISE |
Data fall time, data rise time: rise time measured from –100 mV to 100 mV,
10 MSPS ≤ Sampling frequency ≤ 125 MSPS |
0.11 | ns | ||||
tCLKRISE,
tCLKFALL |
Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV,
10 MSPS ≤ Sampling frequency ≤ 125 MSPS |
0.11 | ns |
SAMPLING FREQUENCY (MSPS) | SETUP TIME
(tSU, ns) |
HOLD TIME
(tHO, ns) |
||||
---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |
25 | 2.27 | 2.6 | 2.41 | 2.6 | ||
40 | 1.44 | 1.6 | 1.51 | 1.7 | ||
50 | 1.2 | 1.32 | 1.24 | 1.4 | ||
60 | 0.95 | 1.04 | 0.97 | 1.09 | ||
80 | 0.68 | 0.75 | 0.72 | 0.81 | ||
100 | 0.5 | 0.57 | 0.53 | 0.62 |
SAMPLING FREQUENCY (MSPS) | SETUP TIME
(tSU, ns) |
HOLD TIME
(tHO, ns) |
||||
---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |
25 | 1.1 | 1.24 | 1.19 | 1.34 | ||
40 | 0.66 | 0.72 | 0.74 | 0.82 | ||
50 | 0.48 | 0.55 | 0.54 | 0.64 | ||
60 | 0.35 | 0.41 | 0.42 | 0.51 | ||
80 | 0.17 | 0.24 | 0.3 | 0.38 |