ZHCSJF0 February   2019 ADC3244E

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      fS = 125MSPS、fIN = 10MHz 时的性能
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: AC Performance
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Requirements: General
    9. 7.9  Timing Requirements: LVDS Output
    10. 7.10 Typical Characteristics
    11. 7.11 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 14x Serialization
        2. 9.3.3.2 Two-Wire Interface: 7x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
        1. 9.4.3.1 Improving Wake-Up Time From Global Power-Down
      4. 9.4.4 Internal Dither Algorithm
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
    6. 9.6 Register Maps
      1. 9.6.1 Summary of Special Mode Registers
      2. 9.6.2 Serial Register Description
        1. 9.6.2.1  Register 01h
          1. Table 10. Register 01h Description
        2. 9.6.2.2  Register 03h
          1. Table 11. Register 03h Description
        3. 9.6.2.3  Register 04h
          1. Table 12. Register 04h Description
        4. 9.6.2.4  Register 05h
          1. Table 13. Register 05h Description
        5. 9.6.2.5  Register 06h
          1. Table 14. Register 06h Description
        6. 9.6.2.6  Register 07h
          1. Table 15. Register 07h Description
        7. 9.6.2.7  Register 09h
          1. Table 16. Register 09h Description
        8. 9.6.2.8  Register 0Ah
          1. Table 17. Register 0Ah Description
        9. 9.6.2.9  Register 0Bh
          1. Table 18. Register 0Bh Description
        10. 9.6.2.10 Register 0Eh
          1. Table 19. Register 0Eh Description
        11. 9.6.2.11 Register 0Fh
          1. Table 20. Register 0Fh Description
        12. 9.6.2.12 Register 13h (address = 13h)
          1. Table 21. Register 13h Field Descriptions
        13. 9.6.2.13 Register 15h
          1. Table 23. Register 15h Description
        14. 9.6.2.14 Register 25h
          1. Table 24. Register 25h Description
        15. 9.6.2.15 Register 27h
          1. Table 26. Register 27h Description
        16. 9.6.2.16 Register 41Dh
          1. Table 27. Register 41Dh Description
        17. 9.6.2.17 Register 422h
          1. Table 28. Register 422h Description
        18. 9.6.2.18 Register 434h
          1. Table 29. Register 434h Description
        19. 9.6.2.19 Register 439h
          1. Table 30. Register 439h Description
        20. 9.6.2.20 Register 51Dh
          1. Table 31. Register 51Dh Description
        21. 9.6.2.21 Register 522h
          1. Table 32. Register 522h Description
        22. 9.6.2.22 Register 534h
          1. Table 33. Register 534h Description
        23. 9.6.2.23 Register 539h
          1. Table 34. Register 539h Description
        24. 9.6.2.24 Register 608h
          1. Table 35. Register 608h Description
        25. 9.6.2.25 Register 70Ah
          1. Table 36. Register 70Ah Description
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 接收文档更新通知
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.10 Typical Characteristics

typical values at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted)
ADC3244E D101_SBAS671.gif
SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,
THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc
Figure 1. FFT for 10-MHz Input Signal
(Chopper On, Dither On)
ADC3244E D103_SBAS671.gif
SFDR = 95.9 dBc, SNR = 72.7 dBFS, SINAD = 72.7 dBFS,
THD = 93.6 dBc, HD2 = –100.6 dBc, HD3 = –95.9 dBc
Figure 3. FFT for 70-MHz Input Signal (Dither On)
ADC3244E D105_SBAS671.gif
SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS,
THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc
Figure 5. FFT for 170-MHz Input Signal (Dither On)
ADC3244E D107_SBAS671.gif
SFDR = 76.1 dBc, SNR = 70.8 dBFS, SINAD = 69.8 dBFS,
THD = 74.8 dBc, HD2 = –76.1 dBc, HD3 = –80.9 dBc
Figure 7. FFT for 270-MHz Input Signal (Dither On)
ADC3244E D109_SBAS671.gif
SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS,
THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc
Figure 9. FFT for 450-MHz Input Signal (Dither On)
ADC3244E D111_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 88.3 dBFS,
each tone at –7 dBFS
Figure 11. FFT for Two-Tone Input Signal
ADC3244E D113_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 86.4 dBFS,
each tone at –7 dBFS
Figure 13. FFT for Two-Tone Input Signal
ADC3244E D115_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 15. Intermodulation Distortion vs Input Amplitude
ADC3244E D117_SBAS671.gif
Figure 17. Signal-to-Noise Ratio vs Input Frequency
ADC3244E D119_SBAS671.gif
fIN = 30 MHz
Figure 19. Performance vs Input Amplitude
ADC3244E D121_SBAS671.gif
fIN = 30 MHz
Figure 21. Performance vs Input Common-Mode Voltage
ADC3244E D123_SBAS671.gif
fIN = 170 MHz
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC3244E D125_SBAS671.gif
fIN = 170 MHz
Figure 25. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC3244E D127_SBAS671.gif
fIN = 40 MHz
Figure 27. Performance vs Clock Amplitude
ADC3244E D129_SBAS671.gif
fIN = 30 MHz
Figure 29. Performance vs Clock Duty Cycle
ADC3244E D131_SBAS671.gif
RMS Noise = 1.4 LSBs
Figure 31. Idle Channel Histogram
ADC3244E D002_BAS671.gif
fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP,
SNR = 58.51 dBFS, SINAD = 58.51 dBFS, SFDR = 60.53 dBc, THD = –90.71 dBc, SFDR = 60.53 dBc (non 23)
Figure 33. Power-Supply Rejection Ratio Spectrum
ADC3244E D004_BAS671.gif
fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP,
SNR = 69.72 dBFS, SINAD = 69.66 dBFS, SFDR = 75.66 dBc, THD = –86.98 dBc, SFDR = 75.66 dBc (non 23)
Figure 35. Common-Mode Rejection Ratio Spectrum
ADC3244E D102_SBAS671.gif
SFDR = 91.8 dBc, SNR = 73.5 dBFS, SINAD = 73.4 dBFS,
THD = 87.3 dBc, HD2 = –93.8 dBc, HD3 = –91.8 dBc
Figure 2. FFT for 10-MHz Input Signal
(Chopper On, Dither Off)
ADC3244E D104_SBAS671.gif
SFDR = 90.9 dBc, SNR = 73.3 dBFS, SINAD = 73.1 dBFS,
THD = 87 dBc, HD2 = –90.9 dBc, HD3 = –94.9 dBc
Figure 4. FFT for 70-MHz Input Signal (Dither Off)
ADC3244E D106_SBAS671.gif
SFDR = 89.9 dBc, SNR = 72.8 dBFS, SINAD = 72.6 dBFS,
THD = 87.1 dBc, HD2 = –97.2 dBc, HD3 = –89.9 dBc
Figure 6. FFT for 170-MHz Input Signal (Dither Off)
ADC3244E D108_SBAS671.gif
SFDR = 76.1 dBc, SNR = 71.2 dBFS, SINAD = 70.2 dBFS,
THD = 74.9 dBc, HD2 = –76.1 dBc, HD3 = –81.6 dBc
Figure 8. FFT for 270-MHz Input Signal (Dither Off)
ADC3244E D110_SBAS671.gif
SFDR = 75.3 dBc, SNR = 69.1 dBFS, SINAD = 67.8 dBFS,
THD = 72.7 dBc, HD2 = –76.7 dBc, HD3 = –75.3 dBc
Figure 10. FFT for 450-MHz Input Signal (Dither Off)
ADC3244E D112_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90.8 dBFS,
each tone at –36 dBFS
Figure 12. FFT for Two-Tone Input Signal
ADC3244E D114_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 87.28 dBFS,
each tone at –36 dBFS
Figure 14. FFT for Two-Tone Input Signal
ADC3244E D116_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 16. Intermodulation Distortion vs Input Amplitude
ADC3244E D118_SBAS671.gif
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
ADC3244E D120_SBAS671.gif
fIN = 170 MHz
Figure 20. Performance vs Input Amplitude
ADC3244E D122_SBAS671.gif
fIN = 170 MHz
Figure 22. Performance vs Input Common-Mode Voltage
ADC3244E D124_SBAS671.gif
fIN = 170 MHz
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC3244E D126_SBAS671.gif
fIN = 170 MHz
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC3244E D128_SBAS671.gif
fIN = 150 MHz
Figure 28. Performance vs Clock Amplitude
ADC3244E D130_SBAS671.gif
fIN = 150 MHz
Figure 30. Performance vs Clock Duty Cycle
ADC3244E D001_BAS671.gif
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
Figure 32. Power-Supply Rejection Ratio vs
Test Signal Frequency
ADC3244E D003_BAS671.gif
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
Figure 34. Common-Mode Rejection Ratio vs
Test Signal Frequency
ADC3244E D009_SBAS672.gif
Figure 36. Power vs Sampling Frequency (1-Wire Mode)