ZHCSJF0 数据表 | 德州仪器 TI.com.cn

ZHCSJF0 February 2019 ADC3244E

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9.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC3244E are driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 43, Figure 44, and Figure 45. See Figure 46 for details regarding the internal clock buffer.

NOTE: R_T = termination resistor, if necessary.

Figure 43. Differential Sine-Wave Clock Driving Circuit

Figure 44. LVDS Clock Driving Circuit

Figure 45. LVPECL Clock Driving Circuit

NOTE: C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 46. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 47. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

Figure 47. Single-Ended Clock Driving Circuit

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9.3.2 Clock Input