ZHCSHT7E April   2019  – February 2023 ADC12DJ5200RF

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Comparison
      2. 7.3.2  Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3  ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Overrange Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4  Temperature Monitoring Diode
      5. 7.3.5  Timestamp
      6. 7.3.6  Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7  Programmable FIR Filter (PFIR)
        1. 7.3.7.1 Dual Channel Equalization
        2. 7.3.7.2 Single Channel Equalization
        3. 7.3.7.3 Time Varying Filter
      8. 7.3.8  Digital Down Converters (DDC)
        1. 7.3.8.1 Rounding and Saturation
        2. 7.3.8.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.8.2.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.8.2.2 NCO Selection
          3. 7.3.8.2.3 Basic NCO Frequency Setting Mode
          4. 7.3.8.2.4 Rational NCO Frequency Setting Mode
          5. 7.3.8.2.5 NCO Phase Offset Setting
          6. 7.3.8.2.6 NCO Phase Synchronization
        3. 7.3.8.3 Decimation Filters
        4. 7.3.8.4 Output Data Format
        5. 7.3.8.5 Decimation Settings
          1. 7.3.8.5.1 Decimation Factor
          2. 7.3.8.5.2 DDC Gain Boost
      9. 7.3.9  JESD204C Interface
        1. 7.3.9.1 Transport Layer
        2. 7.3.9.2 Scrambler
        3. 7.3.9.3 Link Layer
        4. 7.3.9.4 8B/10B Link Layer
          1. 7.3.9.4.1 Data Encoding (8B/10B)
          2. 7.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.9.4.3 Code Group Synchronization (CGS)
          4. 7.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.9.4.5 Frame and Multiframe Monitoring
        5. 7.3.9.5 64B/66B Link Layer
          1. 7.3.9.5.1 64B/66B Encoding
          2. 7.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.9.5.4 Initial Lane Alignment
          5. 7.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.9.6 Physical Layer
          1. 7.3.9.6.1 SerDes Pre-Emphasis
        7. 7.3.9.7 JESD204C Enable
        8. 7.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 7.3.9.9 Operation in Subclass 0 Systems
      10. 7.3.10 Alarm Monitoring
        1. 7.3.10.1 Clock Upset Detection
        2. 7.3.10.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
        5. 7.4.4.5 Dual DDC and Redundant Data Mode
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 ADC12DJ5200RF
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 146
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.8.3 Decimation Filters

The decimation filters are arranged to provide a programmable overall decimation of 4 or 8. All decimation filters operate on complex data (from the complex digital mixer) and the outputs have a resolution of 15 bits. The decimation filters are implemented as linear phase finite impulse response (FIR) filters. Table 7-12 lists the effective output sample rates, available signal bandwidths, output formats, and stop-band attenuation for each decimation mode.

Table 7-12 Output Sample Rates and Signal Bandwidths
DECIMATION SETTINGƒ(DEVCLK)OUTPUT FORMAT
OUTPUT RATE (MSPS)MAX ALIAS PROTECTED SIGNAL BANDWIDTH (MHz)STOP-BAND ATTENUATIONPASS-BAND RIPPLE
No decimation (DDC bypass)ƒ(DEVCLK)ƒ(DEVCLK) / 2—< ±0.001 dBReal signal,
12-bit data
Decimate-by-4ƒ(DEVCLK) / 40.8 × ƒ(DEVCLK) / 4> 90 dB< ±0.001 dBComplex signal,
15-bit data
Decimate-by-8ƒ(DEVCLK) / 80.8 × ƒ(DEVCLK) / 8> 90 dB< ±0.001 dBComplex signal,
15-bit data
Decimate-by-16ƒ(DEVCLK) / 160.8 × ƒ(DEVCLK) / 16> 90 dB< ±0.001 dBComplex signal,
15-bit data
Decimate-by-32ƒ(DEVCLK) / 320.8 × ƒ(DEVCLK) / 32> 90 dB< ±0.001 dBComplex signal,
15-bit data

#SLVSEN93800 to #SLVSEN94664_32XZ provide the composite decimation filter responses. The black portion of the trace shows the pass-band region, or alias-protected region, of the response. The red portion of the trace shows the transition region of the response as well as any frequency regions that will alias into the transition region. The transition region is not alias protected and therefore desired signals should only be placed in the pass-band region of the filter response. The blue portion of the trace shows the frequency regions that will alias into the pass-band after decimation and therefore define the stop-band region of the frequency response. The stop-band attenuation is defined to sufficient filter any undesired images or signals to prevent them from aliasing into the desired pass-band. Use analog filtering before the analog inputs (INA± or INB±) for additional attenuation of signals that fall within this band or to sufficiently reduce signals at the ADC inputs that may produce harmonics, interleaving spurs or other undesired spurious signals that will alias into the desired signal band (before the complex mixing and decimation operations).

GUID-F48024E6-E9BD-49DF-B5E9-5EE1204E623C-low.gifFigure 7-11 Decimate-by-4 Composite Response
GUID-8D26F336-209F-4BA8-AB6B-A3946E7B8F9F-low.gifFigure 7-13 Decimate-by-8 Composite Response
GUID-C48C2940-335C-4F7D-B6BA-E4DAEFF9DCB3-low.gifFigure 7-15 Decimate-by-16 Composite Response
GUID-0633D371-5E72-476C-B0F2-8EAD8F8CD72E-low.gifFigure 7-17 Decimate-by-32 Composite Response
GUID-AD7FA018-E112-4C87-ADFA-68D2AEFB51DA-low.gifFigure 7-12 Decimate-by-4 Composite Zoomed Pass-Band Response
GUID-020C3277-AAEC-4A4B-A762-4041637900D6-low.gifFigure 7-14 Decimate-by-8 Composite Zoomed Pass-Band Response
GUID-C30B9E5A-88B6-46BF-ACD1-702FD3DBC451-low.gifFigure 7-16 Decimate-by-16 Composite Zoomed Pass-Band Response
GUID-E99E691E-1113-4AA5-B41E-8E353462E2D6-low.gifFigure 7-18 Decimate-by-32 Composite Zoomed Pass-Band Response

For maximum efficiency, a group of high-speed filter blocks are implemented with specific blocks used for each decimation setting to achieve the composite responses illustrated in #SLVSEN93800 to #SLVSEN94664_32XZ. Table 7-13 describes the combination of filter blocks used for each decimation setting and Table 7-14 lists the coefficient details and decimation factor of each filter block. The coefficients are symmetric with the center tap indicated by bold text.

Table 7-13 Decimation Mode Filter Usage
DECIMATION SETTINGFILTER BLOCKS USED (Listed in Order of Operation)
4CS40, CS80
8CS20, CS40, CS80
16CS10, CS20, CS40, CS80
32CS5, CS10, CS20, CS40, CS80
Table 7-14 Filter Coefficient Details
FILTER COEFFICIENT SET (Decimation Factor of Filter, Scale factor)
CS5 (2, 2-5)CS10 (2, 2-11)CS20 (2, 2-14)CS40 (2, 2-17)CS80 (2, 2-19)
–1–1–65–65109109–327–327–37–37
0000000000
99577577–837–83722312231118118
161024000000
48244824–8881–8881–291–291
81920000
3974239742612612
6553600
–1159–1159
00
20312031
00
–3356–3356
00
53085308
00
–8140–8140
00
1228412284
00
–18628–18628
00
2945529455
00
–53191–53191
00
166059166059
262144