SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 12-762 lists the memory-mapped registers for an ECC Aggregator (ECC_AGGR).
Offset | Acronym | Register Name |
---|---|---|
ECC Wrapper Registers | ||
10h | Section 10.4.4.1 | ECC Wrapper Revision Register |
14h | Section 10.4.4.2 | ECC RAM Control Register |
18h | Section 10.4.4.3 | ECC RAM Error Control 1 Register |
1Ch | Section 10.4.4.4 | ECC RAM Error Control 2 Register |
20h | Section 10.4.4.5 | ECC RAM Error Status 1 Register |
24h | Section 10.4.4.6 | ECC RAM Error Status 2 Register |
28h | Section 10.4.4.7 | ECC RAM Error Status 3 Register |
Interconnect ECC Component Registers | ||
10h | Section 10.4.4.8 | Interconnect ECC Component Revision Register |
14h | Section 10.4.4.9 | Interconnect ECC Component Control Register |
18h | Section 10.4.4.10 | Interconnect ECC Component Error Control 1 Register |
1Ch | Section 10.4.4.11 | Interconnect ECC Component Error Control 2 Register |
20h | Section 10.4.4.12 | Interconnect ECC Component Error Status 1 Register |
24h | Section 10.4.4.13 | Interconnect ECC Component Error Status 2 Register |
ECC_WRAP_REV is shown in Figure 12-551 and described in Table 12-763.
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ECC Wrapper Revision Register
Revision parameters.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66A49A02h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66A49A02h | TI internal data. |
ECC_CTRL is shown in Figure 12-552 and described in Table 12-764.
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ECC RAM Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHECK_SVBUS_TIMEOUT | ||||||
R-0h | R/W-1h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHECK_PARITY | ERROR_ONCE | FORCE_N_ROW | FORCE_DED | FORCE_SEC | ENABLE_RMW | ECC_CHECK | ECC_ENABLE |
R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-1h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0 | Reserved |
8 | CHECK_SVBUS_TIMEOUT | R/W | 1h | Enable ECC serial interface timeout mechanism 0h - Timeout mechanism disabled 1h - Timeout mechanism enabled |
7 | CHECK_PARITY | R/W | 1h | Enables parity checking on internal data 0h - Parity checking disabled 1h - Parity checking enabled |
6 | ERROR_ONCE | R/W | 0h | Force error only once. If this bit is set to 1h, the FORCE_SEC/FORCE_DED injects an error to the specified row only once. The FORCE_SEC bit is cleared the cycle after the error is generated. For double-bit errors, the FORCE_DED bit is cleared the cycle following the double-bit error. Any subsequent reads do not force an error. |
5 | FORCE_N_ROW | R/W | 0h | Force error on any RAM read Force single or double-bit error on the next RAM access. For write through mode this applies to writes as well as reads. |
4 | FORCE_DED | R/W | 0h | Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is 1h. For write through mode this applies to writes as well as reads. |
3 | FORCE_SEC | R/W | 0h | Force single-bit error. Cleared the cycle following the error if ERROR_ONCE is 1h. For write through mode this applies to writes as well as reads. |
2 | ENABLE_RMW | R/W | 1h | Enable read-modify-write on partial word writes. 0h - Read-modify-write disabled 1h - Read-modify-write enabled Note: NOTE: If disabled, ECC detection and correction does no longer work and if re-enabled the RAM contents must all be rewritten to correct ECC codes. The reset value of this bit is 0h in inject only mode and 1h in ECC mode. |
1 | ECC_CHECK | R/W | 1h | Enable ECC check. 0h - ECC check disabled 1h - ECC check enabled Note: NOTE: ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are 0h. The reset value of this bit is 0h in inject only mode and 1h in ECC mode. |
0 | ECC_ENABLE | R/W | 1h | Enable ECC generation. 0h - ECC generation disabled 1h - ECC generation enabled |
ECC_ERR_CTRL1 is shown in Figure 12-553 and described in Table 12-765.
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ECC RAM Error Control 1 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_ROW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ECC_ROW | R/W | 0h | Row address where single or double-bit error needs to be applied. This is ignored if ECC_CTRL[5] FORCE_N_ROW bit is set to 1h. |
ECC_ERR_CTRL2 is shown in Figure 12-554 and described in Table 12-766.
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ECC RAM Error Control 2 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_BIT2 | ECC_BIT1 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ECC_BIT2 | R/W | 0h | Data bit that needs to be flipped if double-bit error has to be forced. The ECC_CTRL[4] FORCE_DED bit must be set to 1h for these values to take affect. |
15-0 | ECC_BIT1 | R/W | 0h | Data bit that needs to be flipped if single-bit error has to be forced. The ECC_CTRL[3] FORCE_SEC bit must be set to 1h for these values to take affect. |
ECC_ERR_STAT1 is shown in Figure 12-555 and described in Table 12-767.
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ECC RAM Error Status 1 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ECC_BIT1 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ECC_BIT1 | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLR_CTRL_REG_ERR | CLR_PARITY_ERR | CLR_ECC_OTHER | CLR_ECC_DED | CLR_ECC_SEC | |||
R/W1C-0h | R/W-0h | R/W1C-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTR_REG_ERR | PARITY_ERR | ECC_OTHER | ECC_DED | ECC_SEC | |||
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ECC_BIT1 | R | 0h | Indicates the bit position in the RAM data that is in error. For example, a value of 1h indicates that bit [1] in the RAM data is in error. This is valid only for single-bit errors. Note: NOTE: Not used in inject only mode. Always read as 0h. |
15 | CLR_CTRL_REG_ERR | R/W1C | 0h | Clear the CTR_REG_ERR bit. A write of 1h clears this bit and the CTR_REG_ERR bit, but if the redundancy protected bits in the ECC_CTRL register have not been written to a known state to correct the error, this flag is immediately set again. |
14-13 | CLR_PARITY_ERR | R/W | 0h | A write of a non-zero value to this field decrements the CLR_ECC_DED and ECC_DED fields by that value. If the value written is less than the current one, the non-correctable interrupt (ECC_DED_INT) stays asserted. If the value to decrement is more than the current value, the result is 0. 0h - No parity errors have occurred 1h - 1 parity error has occurred 2h - 2 parity errors have occurred 3h - 3 or more parity errors have occurred |
12 | CLR_ECC_OTHER | R/W1C | 0h | Clear other error status. 1h indicates a successive single-bit error. Writing 1h clears the status bit. |
11-10 | CLR_ECC_DED | R/W | 0h | A write of a non-zero value to this field decrements it and the ECC_DED field by that value. If the value written is less than the current one, the non-correctable interrupt (ECC_DED_INT) stays asserted. If the value to decrement is more than the current value, the result is 0. 0h - No double-bit errors have occurred 1h - 1 double-bit has error occurred 2h - 2 double-bit have errors occurred 3h - 3 or more double-bit errors have occurred Note: NOTE: Not used in inject only mode. Always read as 0h. |
9-8 | CLR_ECC_SEC | R/W | 0h | A write of a non-zero value to this field decrements it and the ECC_SEC field by that value. If the value written is less than the current one, the correctable interrupt (ECC_SEC_INT) stays asserted. If the value to decrement is more than the current value, the result is 0. 0h - No single-bit errors have occurred 1h - 1 single-bit has occurred 2h - 2 single-bit have occurred 3h - 3 or more single-bit have occurred Note: NOTE: Not used in inject only mode. Always read as 0h. |
7 | CTR_REG_ERR | R/W1S | 0h | Indicates that a redundancy protected bit in the ECC_CTRL register has been flipped. This means that the redundancy logic have detected a state where not all values are the same and has defaulted to the reset state. Software needs to re-write these registers to a known state. A write of 1h sets this bit. 0h - Bit not flipped 1h - Bit flipped |
6-5 | PARITY_ERR | R/W1S | 0h | 2-bit saturating counter for the number of parity errors that have occurred since last cleared. This is also a status set register and a non-zero value sets the level interrupt. Software can also write a value to the CLR_PARITY_ERR field to decrement this counter. 0h - No parity errors have occurred 1h - 1 parity error has occurred 2h - 2 parity errors have occurred 3h - 3 or more parity errors have occurred |
4 | ECC_OTHER | R/W1S | 0h | 1h - Indicates that successive single-bit errors have occurred while a write-back is still pending. Software can also write 1h to set the pending status and write 1h to the corresponding clear bit to clear the status. Note: NOTE: Not used in inject only mode. Always read as 0h. |
3-2 | ECC_DED | R/W | 0h | 2-bit saturating counter for the number of double-bit errors that have occurred since last cleared. This is also a status set register and a non-zero value sets the level interrupt. Software can also write a value to the CLR_ECC_SEC field to decrement this counter. 0h - No double-bit errors have occurred 1h - 1 double-bit has error occurred 2h - 2 double-bit have errors occurred 3h - 3 or more double-bit errors have occurred Note: NOTE: Not used in inject only mode. Always read as 0h. |
1-0 | ECC_SEC | R/W | 0h | 2-bit saturating counter for the number of single-bit errors that have occurred since last cleared. This is also a status set register and a non-zero value sets the level interrupt. Software can also write a value to the CLR_ECC_SEC field to decrement this counter. 0h - No single-bit errors have occurred 1h - 1 single-bit has occurred 2h - 2 single-bit have occurred 3h - 3 or more single-bit have occurred Note: NOTE: Not used in inject only mode. Always read as 0h. |
ECC_ERR_STAT2 is shown in Figure 12-556 and described in Table 12-768.
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ECC RAM Error Status 2 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_ROW | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ECC_ROW | R | 0h | Row address where the single or double-bit error has occurred. Note: NOTE: Not used in inject only mode. Always read as 0h. |
ECC_ERR_STAT3 is shown in Figure 12-557 and described in Table 12-769.
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ECC RAM Error Status 3 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLR_SVBUS_TIMEOUT_ERR | RESERVED | |||||
R-0h | R/W1C-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SVBUS_TIMEOUT_ERR | WB_PEND | |||||
R-0h | R/W1S-0h | R-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0 | Reserved |
9 | CLR_SVBUS_TIMEOUT_ERR | R/W1C | 0h | Clear ECC serial interface timeout error status 0h - No effect 1h - Clears this bit and the SVBUS_TIMEOUT_ERR bit |
8-2 | RESERVED | R | 0 | Reserved |
1 | SVBUS_TIMEOUT_ERR | R/W1S | 0h | ECC serial interface timeout error. Write a 1h to set the flag 0h - No timeout error 1h - Timeout error |
0 | WB_PEND | R | 0h | Delayed write-back pending status. 0h - An ECC data correction write-back is not pending 1h - An ECC data correction write-back is pending Note: NOTE: Not used in inject only mode. Always read as 0h. |
ECC_CBASS_REV is shown in Figure 12-558 and described in Table 12-770.
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Interconnect ECC Component Revision Register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-Xh | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | Xh | TI internal data. |
ECC_CBASS_CTRL is shown in Figure 12-559 and described in Table 12-771.
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Interconnect ECC Component Control Register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ECC_PATTERN | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FORCE_N_BIT | FORCE_DE | FORCE_SE | RESERVED | ECC_CHECK | RESERVED | |
R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-1h | R-0h | |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-8 | ECC_PATTERN | R/W | 0h | Data pattern to be used for injection. 0h = 0s 1h = Fs 2h = As 3h = 5s |
7-6 | RESERVED | R | 0h | Reserved |
5 | FORCE_N_BIT | R/W | 0h | Update injection fields after the injection to setup for the next incremental injection. 0h = Keep current settings after injection 1h = Increment to next bit or group after injection |
4 | FORCE_DE | R/W | 0h | Inject a double bit error when set. Automatically cleared when injection completes. |
3 | FORCE_SE | R/W | 0h | Inject a single bit error when set. Automatically cleared when injection completes. |
2 | RESERVED | R | 0h | Reserved |
1 | ECC_CHECK | R/W | 1h | Enable checkers. 0h = Disabled 1h = Enabled |
0 | RESERVED | R | 0h | Reserved |
ECC_CBASS_ERR_CTRL1 is shown inFigure 12-560 and described in Table 12-772.
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Interconnect ECC Component Error Control 1 Register.
This register allows setting the injection data.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | ECC_BIT1 | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ECC_BIT1 | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ECC_GRP | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_GRP | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24-16 | ECC_BIT1 | R/W | 0h | First bit to inject an error. |
15-0 | ECC_GRP | R/W | 0h | Group of checker to inject. |
ECC_CBASS_ERR_CTRL2 is shown in Figure 12-561 and described in Table 12-773.
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Interconnect ECC Component Error Control 2 Register.
This register allows setting the injection data.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECC_BIT2 | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8-0 | ECC_BIT2 | R/W | 0h | Second bit to inject an error. Only valid if ECC_CBASS_CTRL[4] FORCE_DE is set. |
ECC_CBASS_ERR_STAT1 is shown in Figure 12-562 and described in Table 12-774.
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Interconnect ECC Component Error Status 1 Register.
This register allows reading the captured error data.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ERR_GRP | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ERR_GRP | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INJ_UNC_PEND_CLR | INJ_COR_PEND_CLR | UNC_PEND_CLR | COR_PEND_CLR | ||||
R/WD-0h | R/WD-0h | R/WD-0h | R/WD-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INJ_UNC_PEND | INJ_COR_PEND | UNC_PEND | COR_PEND | ||||
R/WI-0h | R/WI-0h | R/WI-0h | R/WI-0h | ||||
LEGEND: R = Read Only; R/WD = Read/Write to Decrement Field; R/WI = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ERR_GRP | R | 0h | Specific checker that reported the error. |
15-14 | INJ_UNC_PEND_CLR | R/WD | 0h | Number of injected uncorrected pending interrupts (same value as UNC_PEND). Writing decrements INJ_UNC_PEND by that value. |
13-12 | INJ_COR_PEND_CLR | R/WD | 0h | Number of injected corrected pending interrupts (same value as COR_PEND). Writing decrements INJ_COR_PEND by that value. |
11-10 | UNC_PEND_CLR | R/WD | 0h | Number of uncorrected pending interrupts (same value as UNC_PEND). Writing decrements UNC_PEND by that value. |
9-8 | COR_PEND_CLR | R/WD | 0h | Number of corrected pending interrupts (same value as COR_PEND). Writing decrements COR_PEND by that value. |
7-6 | INJ_UNC_PEND | R/WI | 0h | Number of injected uncorrected pending interrupts. Writing increments by that value. |
5-4 | INJ_COR_PEND | R/WI | 0h | Number of injected corrected pending interrupts. Writing increments by that value. |
3-2 | UNC_PEND | R/WI | 0h | Number of uncorrected pending interrupts. Writing increments by that value. |
1-0 | COR_PEND | R/WI | 0h | Number of corrected pending interrupts. Writing increments by that value. |
ECC_CBASS_ERR_STAT2 is shown in Figure 12-563 and described in Table 12-775.
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Interconnect ECC Component Error Status 2 Register.
This register allows reading the captured error data.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERR_TYPE | ERR_BIT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ERR_TYPE | R | 0h | This field is not supported and can read any value and be ignored. |
15-0 | ERR_BIT | R | 0h | Bit that caused the error. Always valid for EDC single bit corrected errors or redundant errors. Identifies parity segment number (but not the exact bit) with a parity error. This field is not valid for EDC double bit errors. |