ZHCSEY3D April   2016  – October 2019 DS90UB914A-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: DS90UB914A-Q1 Deserializer
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Timing Specifications (SCL, SDA) - I2C-Compatible
    7. 7.7 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 7.8 Deserializer Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams and Test Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Frame Format
      2. 9.3.2  Line Rate Calculations for the DS90UB913A/914A
      3. 9.3.3  Deserializer Multiplexer Input
      4. 9.3.4  Error Detection
      5. 9.3.5  Synchronizing Multiple Cameras
      6. 9.3.6  General-Purpose I/O (GPIO) Descriptions
      7. 9.3.7  LVCMOS VDDIO Option
      8. 9.3.8  EMI Reduction
        1. 9.3.8.1 Deserializer Staggered Output
        2. 9.3.8.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
      9. 9.3.9  Pixel Clock Edge Select (TRFB / RRFB)
      10. 9.3.10 Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 DS90UB913A/914A Operation With External Oscillator as Reference Clock
      2. 9.4.2 DS90UB913A/914A Operation With Pixel Clock From Imager as Reference Clock
      3. 9.4.3 MODE Pin on Deserializer
      4. 9.4.4 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      5. 9.4.5 Built-In Self Test
      6. 9.4.6 BIST Configuration and Status
      7. 9.4.7 Sample BIST Sequence
    5. 9.5 Programming
      1. 9.5.1 Programmable Controller
      2. 9.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 9.5.3 I2C Pass-Through
      4. 9.5.4 Slave Clock Stretching
      5. 9.5.5 ID[x] Address Decoder on the Deserializer
      6. 9.5.6 Multiple Device Addressing
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power Over Coax
      2. 10.1.2 Power-Up Requirements and PDB Pin
      3. 10.1.3 AC Coupling
      4. 10.1.4 Transmission Media
      5. 10.1.5 Adaptive Equalizer – Loss Compensation
    2. 10.2 Typical Applications
      1. 10.2.1 Coax Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 STP Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Interconnect Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

RHS Package
48-Pin WQFN
Top View
DS90UB914A-Q1 DS90UB914AQ_PINOUT.gif

Pin Functions: DS90UB914A-Q1 Deserializer

PIN I/O DESCRIPTION
NAME NO.
LVCMOS PARALLEL INTERFACE
ROUT[11:0] 11,12,13,14,
15,16,18,19,
21,22,23,24		 Outputs, LVCMOS Parallel Data Outputs
For 10-bit MODE, parallel outputs ROUT[9:0] are active. ROUT[11:10] are inactive and should not be used. Any unused outputs (including ROUT[11:10]) should be No Connect.
For 12-bit MODE (HF or LF), parallel outputs ROUT[11:0] are active. Any unused outputs should be No Connect.
HSYNC 10 Output, LVCMOS Horizontal SYNC Output. Note: HS transition restrictions: 1. 12-bit Low-Frequency mode: No HS restrictions (raw) 2. 12-bit High-Frequency mode: No HS restrictions (raw) 3. 10-bit mode: HS restricted to no more than one transition per 10 PCLK cycles. Leave open if unused.
VSYNC 9 Output, LVCMOS Vertical SYNC Output. Note: VS transition restrictions: 1. 12-bit Low-Frequency mode: No VS restrictions (raw) 2. 12-bit High-Frequency mode: No VS restrictions (raw) 3. 10-bit mode: VS restricted to no more than one transition per 10 PCLK cycles. Leave open if unused.
PCLK 8 Output, LVCMOS Pixel Clock Output Pin
Strobe edge set by RRFB control register.
In the 12-bit low frequency mode and 10-bit mode, the PCLK will become active before LOCK goes high.
In the 12-bit high frequency mode, the PCLK and LOCK become active at the same time.
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
GPI0[1:0] 27,28 Digital Input/Output, LVCMOS General-purpose input/output pins can be used to control and respond to various commands. They may be configured to be the input signals for the corresponding GPOs on the serializer or they may be configured to be outputs to follow local register settings. Leave open if unused.
GPIO[3:2] 25,26 Digital Input/Output LVCMOS General purpose input/output pins GPO[3:2] can be configured to be input signals for GPOs on the Serializer. In addition they can also be configured to be outputs to follow the local register settings. When the SerDes chipsets are working with an external oscillator, these pins can be configured only to be outputs to follow the local register settings. Leave open if unused.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL 2 Input/Output,
Open Drain		 Clock line for the bidirectional control bus communication
SCL requires an external pullup resistor to VDDIO.
SDA 1 Input/Output,
Open Drain		 Data line for bidirectional control bus communication
SDA requires an external pullup resistor to VDDIO.
MODE 37 Input, analog Device Mode Select
Resistor to Ground and 10-kΩ pullup to 1.8 V rail. The MODE pin on the Deserializer can be used to configure the Serializer and Deserializer to work in different input PCLK range. See details in Table 2.
12– bit low frequency mode – (25 – 50 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 12-bits DATA+2 SYNC. Input PCLK range is from 25 MHz to 50 MHz. Note: No HS/VS restrictions.

12– bit high frequency mode – (37.5 – 75 MHz operation): In this mode, the Serializer and Deserializer can accept up to 12-bits DATA + 2 SYNC. Input PCLK range is from 37.5 MHz to 75 MHz. Note: No HS/VS restrictions.
10–bit mode– (50 – 100 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 10-bits DATA + 2 SYNC. Input PCLK frequency can range from 50 MHz to 100 MHz. Note: HS/VS restricted to no more than one transition per 10 PCLK cycles.
Please refer to Table 2 on how to configure the MODE pin on the Deserializer.
IDx[0:1] 35,34 Input, analog Device ID Address Select
The IDx[0] and IDx[1] pins on the Deserializer are used to assign the I2C slave device address. Resistor to Ground and 10-kΩ pullup to 1.8 V rail. See Table 6
CONTROL AND CONFIGURATION
PDB 30 Input, LVCMOS
w/ pulldown		 Power Down Mode Pin
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in power down mode. When the Deserializer is in power down mode, programmed control register data are NOT retained and reset to default values.
LOCK 48 Output,
LVCMOS		 LOCK Status Output Pin
LOCK = H, PLL is Locked, outputs are active.
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by OSS_SEL control register. May be used as Link Status.
In the 12-bit low frequency mode and 10-bit mode, the PCLK will become active before LOCK goes high.
In the 12-bit high frequency mode, the PCLK and LOCK become active at the same time.
BISTEN 6 Input
LVCMOS w/ pulldown		 BIST Enable Pin
BISTEN=H, BIST Mode is enabled.
BISTEN=L, BIST Mode is disabled.
See Built-In Self Test for more information.
PASS 47 Output,
LVCMOS		 PASS Output Pin
PASS = H, ERROR FREE Transmission.
PASS = L, one or more errors were detected in the received payload.
See Built-In Self Test for more information. Leave Open if unused. Route to test point (pad) recommended.
OEN 5 Input
LVCMOS w/ pulldown		 Output Enable Input
Refer to Table 3.
OSS_SEL 4 Input
LVCMOS w/ pulldown		 Output Sleep State Select Pin
Refer to Table 3.
SEL 46 Input
LVCMOS w/ pulldown		 MUX Select Line
SEL = L, RIN0+/- input. This selects input A as the active channel on the Deserializer.
SEL = H, RIN1+/- input. This selects input B as the active channel on the Deserializer.
FPD–Link III INTERFACE
RIN0+ 41 Input/Output, CML Noninverting Differential input, bidirectional control channel. The IO must be AC-coupled with a 0.1-µF capacitor. Leave open if unused.
RIN0- 42 Input/Output, CML Inverting Differential input, bidirectional control channel. The IO must be AC-coupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect, a 0.047-µF, AC-coupling capacitor should be placed in series with a 50-Ω resistor before terminating to GND. Leave open if unused.
RIN1+ 32 Input/Output, CML Noninverting Differential input, bidirectional control channel. The IO must be AC-coupled with a 0.1-µF capacitor. Leave open if unused.
RIN1- 33 Input/Output, CML Inverting Differential input, bidirectional control channel. The IO must be AC coupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect, a 0.047-µF, AC-coupling capacitor should be placed in series with a 50-Ω resistor before terminating to GND. Leave open if unused.
RES 43,44 — Reserved. This pin must always be tied low.
CMLOUTP/N 38,39 Output, CML Route to test point or leave open if unused.
POWER AND GROUND (1)
VDDIO1/2/3 29, 20, 7 Power, Digital LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to a 1.8 V ±5% or 3.3 V ±10%.
VDDD 17 Power, Digital Digital Core Power, 1.8 V ±5%.
VDDSSCG 3 Power, Analog SSCG PLL Power, 1.8 V ±5%.
VDDR 36 Power, Analog Rx Analog Power, 1.8 V ±5%.
VDDCML0/1 40,31 Power, Analog CML and Bidirectional control channel Drive Power, 1.8 V ±5%.
VDDPLL 45 Power, Analog PLL Power, 1.8 V ±5%.
VSS DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias.