ZHCSEY3D April   2016  – October 2019 DS90UB914A-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: DS90UB914A-Q1 Deserializer
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Timing Specifications (SCL, SDA) - I2C-Compatible
    7. 7.7 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 7.8 Deserializer Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams and Test Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Frame Format
      2. 9.3.2  Line Rate Calculations for the DS90UB913A/914A
      3. 9.3.3  Deserializer Multiplexer Input
      4. 9.3.4  Error Detection
      5. 9.3.5  Synchronizing Multiple Cameras
      6. 9.3.6  General-Purpose I/O (GPIO) Descriptions
      7. 9.3.7  LVCMOS VDDIO Option
      8. 9.3.8  EMI Reduction
        1. 9.3.8.1 Deserializer Staggered Output
        2. 9.3.8.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
      9. 9.3.9  Pixel Clock Edge Select (TRFB / RRFB)
      10. 9.3.10 Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 DS90UB913A/914A Operation With External Oscillator as Reference Clock
      2. 9.4.2 DS90UB913A/914A Operation With Pixel Clock From Imager as Reference Clock
      3. 9.4.3 MODE Pin on Deserializer
      4. 9.4.4 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      5. 9.4.5 Built-In Self Test
      6. 9.4.6 BIST Configuration and Status
      7. 9.4.7 Sample BIST Sequence
    5. 9.5 Programming
      1. 9.5.1 Programmable Controller
      2. 9.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 9.5.3 I2C Pass-Through
      4. 9.5.4 Slave Clock Stretching
      5. 9.5.5 ID[x] Address Decoder on the Deserializer
      6. 9.5.6 Multiple Device Addressing
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power Over Coax
      2. 10.1.2 Power-Up Requirements and PDB Pin
      3. 10.1.3 AC Coupling
      4. 10.1.4 Transmission Media
      5. 10.1.5 Adaptive Equalizer – Loss Compensation
    2. 10.2 Typical Applications
      1. 10.2.1 Coax Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 STP Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Interconnect Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.8 Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
MIN NOM MAX UNIT
tRCP Receiver Output Clock Period(4) 10-bit mode
50 MHz – 100 MHz 		PCLK (Figure 8) 10 T 20 ns
12-bit high frequency mode
37.5 MHz - 75MHz		 13.33 T 26.67
12-bit low frequency mode
25 MHz - 50MHz		 20 T 40
tPDC PCLK Duty Cycle 10-bit mode
50 MHz – 100 MHz 		PCLK 45% 50% 55%
12-bit high frequency mode
37.5 MHz - 75MHz		 40% 50% 60%
12-bit low frequency mode
25 MHz - 50MHz		 40% 50% 60%
tCLH LVCMOS Low-to-High Transition Time VDDIO: 1.71 V to 1.89 V or 3 V to 3.6 V, CL = 8 pF
(lumped load)
Default Registers (Figure 6)(1) 		PCLK 1.3 2 2.8 ns
tCHL LVCMOS High-to-Low Transition Time 1.3 2 2.8
tDLH LVCMOS Low-to-High Transition Time VDDIO: 1.71 V to 1.89 V or 3 V to 3.6 V, CL = 8 pF
(lumped load)
Default Registers (Figure 6)(1) 		ROUT[11:0], HS, VS 1 2.5 4 ns
tDHL LVCMOS High-to-Low Transition Time 1 2.5 4
tROS ROUT Setup
Data to PCLK (4) 		VDDIO: 1.71 V to 1.89 V or 3 V to 3.6 V, CL = 8 pF (lumped load), Default Registers (Figure 8) ROUT[11:0], HS, VS 0.38T 0.5T
tROH ROUT Hold
Data to PCLK (4) 		0.38T 0.5T
tDD Deserializer Delay(4) Default Registers
Register 0x03h b[0] (RRFB = 1)
(Figure 7)(1) 		10–bit mode
50 - 100 MHz		 154T 158T
12–bit low frequency mode
25 - 50 MHz		 73T 75T
12–bit high frequency mode
37.5 - 75 MHz		 109T 112T
tDDLT Deserializer Data Lock Time With Adaptive Equalization (Figure 5) 10–bit mode
50 - 100 MHz		 15 22 ms
12–bit low frequency mode
25 - 50 MHz		 15 22
12–bit high frequency mode
37.5 - 75 MHz		 15 22
tRCJ Receiver Clock Jitter PCLK
SSCG[3:0] = OFF(1) 		10–bit mode
PCLK = 100 MHz		 20 30 ps
12–bit low frequency mode, PCLK = 50 MHz 22 35
12–bit high frequency mode, PCLK = 75 MHz 45 90
tDPJ Deserializer Period Jitter PCLK
SSCG[3:0] = OFF(1)(2) 		10–bit mode
PCLK = 100 MHz		 170 815 ps
12–bit low frequency mode, PCLK = 50 MHz 180 330
12–bit high frequency mode, PCLK = 75 MHz 300 515
tDCCJ Deserializer Cycle-to-Cycle Clock Jitter PCLK
SSCG[3:0] = OFF(1)(3) 		10–bit mode
PCLK = 100 MHz		 440 1760 ps
12–bit low frequency mode, PCLK = 50 MHz 460 730
12–bit high frequency mode, PCLK = 75 MHz 565 985
fdev Spread Spectrum Clocking Deviation Frequency LVCMOS Output Bus
SSC[3:0] = ON (Figure 11)(1) 		25 MHz – 100 MHz ±0.5% to ±1.5%
fmod Spread Spectrum Clocking Modulation Frequency 25 MHz – 100 MHz 5 to 50 kHz
(1) Specification is verified by characterization and is not tested in production.
(2) tDPJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(3) tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
(4) T is the period of the PCLK.
(5) To ensure optimum device functionality, It is recommended to NOT write to any RESERVED registers.