ZHCSEY3D April   2016  – October 2019 DS90UB914A-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: DS90UB914A-Q1 Deserializer
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Timing Specifications (SCL, SDA) - I2C-Compatible
    7. 7.7 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 7.8 Deserializer Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams and Test Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Frame Format
      2. 9.3.2  Line Rate Calculations for the DS90UB913A/914A
      3. 9.3.3  Deserializer Multiplexer Input
      4. 9.3.4  Error Detection
      5. 9.3.5  Synchronizing Multiple Cameras
      6. 9.3.6  General-Purpose I/O (GPIO) Descriptions
      7. 9.3.7  LVCMOS VDDIO Option
      8. 9.3.8  EMI Reduction
        1. 9.3.8.1 Deserializer Staggered Output
        2. 9.3.8.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
      9. 9.3.9  Pixel Clock Edge Select (TRFB / RRFB)
      10. 9.3.10 Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 DS90UB913A/914A Operation With External Oscillator as Reference Clock
      2. 9.4.2 DS90UB913A/914A Operation With Pixel Clock From Imager as Reference Clock
      3. 9.4.3 MODE Pin on Deserializer
      4. 9.4.4 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      5. 9.4.5 Built-In Self Test
      6. 9.4.6 BIST Configuration and Status
      7. 9.4.7 Sample BIST Sequence
    5. 9.5 Programming
      1. 9.5.1 Programmable Controller
      2. 9.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 9.5.3 I2C Pass-Through
      4. 9.5.4 Slave Clock Stretching
      5. 9.5.5 ID[x] Address Decoder on the Deserializer
      6. 9.5.6 Multiple Device Addressing
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power Over Coax
      2. 10.1.2 Power-Up Requirements and PDB Pin
      3. 10.1.3 AC Coupling
      4. 10.1.4 Transmission Media
      5. 10.1.5 Adaptive Equalizer – Loss Compensation
    2. 10.2 Typical Applications
      1. 10.2.1 Coax Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 STP Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Interconnect Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.4.4 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)

When PDB is driven HIGH, the Deserializer’s CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW (depending on the value of the OEN setting). After the DS90UB914A-Q1 completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the parallel bus and PCLK outputs. The states of the outputs are based on the OEN and OSS_SEL setting (Table 3). See Figure 10.

Table 3. Output States

INPUTS OUTPUTS
SERIAL INPUTS PDB OEN OSS_SEL LOCK PASS DATA, GPIO CLK
X 0 X X Z Z Z Z
X 1 0 0 L or H L L L
X 1 0 1 L or H Z Z Z
Static 1 1 0 L L L L/Osc
(Register Bit Enable)
Static 1 1 1 L Previous State L L
Active 1 1 0 H L L L
Active 1 1 1 H Valid Valid Valid