ZHCSEY3D April   2016  – October 2019 DS90UB914A-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: DS90UB914A-Q1 Deserializer
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Timing Specifications (SCL, SDA) - I2C-Compatible
    7. 7.7 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 7.8 Deserializer Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams and Test Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Frame Format
      2. 9.3.2  Line Rate Calculations for the DS90UB913A/914A
      3. 9.3.3  Deserializer Multiplexer Input
      4. 9.3.4  Error Detection
      5. 9.3.5  Synchronizing Multiple Cameras
      6. 9.3.6  General-Purpose I/O (GPIO) Descriptions
      7. 9.3.7  LVCMOS VDDIO Option
      8. 9.3.8  EMI Reduction
        1. 9.3.8.1 Deserializer Staggered Output
        2. 9.3.8.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
      9. 9.3.9  Pixel Clock Edge Select (TRFB / RRFB)
      10. 9.3.10 Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 DS90UB913A/914A Operation With External Oscillator as Reference Clock
      2. 9.4.2 DS90UB913A/914A Operation With Pixel Clock From Imager as Reference Clock
      3. 9.4.3 MODE Pin on Deserializer
      4. 9.4.4 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      5. 9.4.5 Built-In Self Test
      6. 9.4.6 BIST Configuration and Status
      7. 9.4.7 Sample BIST Sequence
    5. 9.5 Programming
      1. 9.5.1 Programmable Controller
      2. 9.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 9.5.3 I2C Pass-Through
      4. 9.5.4 Slave Clock Stretching
      5. 9.5.5 ID[x] Address Decoder on the Deserializer
      6. 9.5.6 Multiple Device Addressing
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power Over Coax
      2. 10.1.2 Power-Up Requirements and PDB Pin
      3. 10.1.3 AC Coupling
      4. 10.1.4 Transmission Media
      5. 10.1.5 Adaptive Equalizer – Loss Compensation
    2. 10.2 Typical Applications
      1. 10.2.1 Coax Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 STP Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Interconnect Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.6 Register Maps

In the register definitions under the TYPE and DEFAULT heading, the following definitions apply:

  • R = Read only access
  • R/W = Read / Write access
  • R/RC = Read only access, Read to Clear
  • (R/W)/SC = Read / Write access, Self-Clearing bit
  • (R/W)/S = Read / Write access, Set based on strap pin configuration at startup
  • LL = Latched Low and held until read
  • LH = Latched High and held until read
  • S = Set based on strap pin configuration at startup

Table 7. DS90UB914A-Q1 Control Registers(5)

ADDR (HEX) NAME BITS FIELD TYPE DEFAULT DESCRIPTION
0x00 I2C Device ID 7:1 DEVICE ID R/W 0xC0'h
(1100_0000'b)		 7-bit address of Deserializer; 0x60'h.
(110_0000'b) default
0 Deserializer ID Select R/W 0: Deserializer Device ID is set from ID[x].
1: Register I2C Device ID overrides ID[x].
0x01 Reset 7:6 RSVD R/W 0x0 Reserved.
5 ANAPWDN R/W 0 This register can be set only through local I2C access.
1: Analog power down: Powers down the analog block in the Serializer.
0: No effect.
4:3 RSVD R/W 0x0 Reserved.
2 BC Enable R/W 1 Back Channel Enable
0: Disable
1: Enable
1 Digital Reset 1 R/W 0 Digital Reset Resets the entire digital block except registers. This bit is self-clearing.
1: Reset.
0: No effect.
0 Digital Reset 0 R/W 0 Digital Reset Resets the entire digital block including registers. This bit is self-clearing.
1: Reset.
0: No effect.
0x02 General Configuration 0 7:6 RSVD R/W 0x0 Reserved.
5 Auto-Clock R/W 0 1: Output PCLK or OSC clock when not LOCKED.
0: Only PCLK.
4 SSCG LFMODE R/W 0 1: Selects 8x mode for 10-18 MHz frequency range in SSCG.
0: SSCG running at 4X mode.
3:0 SSCG R/W 0 SSCG Select.
0000: Normal Operation, SSCG OFF.
0001: fmod (Hz) PCLK/2168, fdev ±0.50%.
0010: fmod (Hz) PCLK/2168, fdev ±1.00%.
0011: fmod (Hz) PCLK/2168, fdev ±1.50%.
0100: fmod (Hz) PCLK/2168, fdev ±2.00%.
0101: fmod (Hz) PCLK/1300, fdev ±0.50%.
0110: fmod (Hz) PCLK/1300, fdev ±1.00%.
0111: fmod (Hz) PCLK/1300, fdev ±1.50%.
1000: fmod (Hz) PCLK/1300, fdev ±2.00%.
1001: fmod (Hz) PCLK/868, fdev ±0.50%.
1010: fmod (Hz) PCLK/868, fdev ±1.00%.
1011: fmod (Hz) PCLK/868, fdev ±1.50%.
1100: fmod (Hz) PCLK/868, fdev ±2.00%.
1101: fmod (Hz) PCLK/650, fdev ±0.50%.
1110: fmod (Hz) PCLK/650, fdev ±1.00%.
1111: fmod (Hz) PCLK/650, fdev ±1.50%.
Note: This register should be changed only after disabling SSCG.
0x03 General Configuration 1 7 RX Parity Checker Enable R/W 1 Forward Channel Parity Checker Enable.
1: Enable.
0: Disable.
6 TX CRC Checker Enable R/W 1 Back Channel CRC Generator Enable.
1: Enable.
0: Disable.
5 VDDIO Control R/W 1 Auto voltage control.
1: Enable (auto detect mode).
0: Disable.
4 VDDIO Mode R/W 0 VDDIO voltage set.
1: 3.3 V
0: 1.8 V
3 I2C Pass-Through R/W 1 I2C Pass-Through Mode.
1: Pass-Through Enabled. SER Alias 0x07 and Slave Alias 0x09- 0x17.
0: Pass-Through Disabled.
2 AUTO ACK R/W 0 Automatically Acknowledge I2C Remote Write When enabled, I2C writes to the Serializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately acknowledged without waiting for the Serializer to acknowledge the write. The accesses are then remapped to address specified in 0x06. This allows I2C bus without LOCK.
1: Enable.
0: Disable.
1 Parity Error Reset R/W 0 Parity Error Reset, This bit is NOT self-clearing.
1: Parity Error Reset.
0: No effect.
0 RRFB R/W 1 Pixel Clock Edge Select.
1: Parallel Interface Data is strobed on the Rising Clock Edge.
0: Parallel Interface Data is strobed on the Falling Clock Edge.
0x04 EQ Feature Control 7:4 EQ level - when AEQ bypass is enabled EQ setting is provided by this register R/W 0000 Equalization gain values listed below are @ maximum line rate (1.4 Gbps).
0000 = ~16.5 dB (minimum)
0001 = ~19.0 dB
0011 = ~20.5 dB
0111 = ~22.0 dB
1111 = ~23.0 dB (maximum)
3:0 RSVD R/W 0x0 Reserved.
0x05 Forward Channel Low Frequency Gain 7:0 LF GAIN R/W 0x00 0x00: Default
0xC0: Beneficial for shorter cable (< 6 meter) applications that have system impedance mismatch. Increases signal-to-noise ratio (SNR) at low frequencies on forward channel to alleviate impedance mismatch.
0x06 SER ID 7:1 Remote ID R/W 0x00'h 7-bit Serializer Device ID Configures the I2C Slave ID of the remote Serializer. A value of 0 in this field disables I2C access to the remote Serializer. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the Bidirectional Control Channel.
0 Freeze Device ID R/W 0 1: Freeze Serializer Device ID Prevent auto-loading of the Serializer Device ID from the Forward Channel. The ID will be frozen at the value written.
0: Update.
0x07 SER Alias 7:1 Serializer Alias ID R/W 0x00'h 7-bit Remote Serializer Device Alias ID Configures the decoder for detecting transactions designated for an I2C Serializer device. The transaction will be remapped to the address specified in the SER ID register. A value of 0 in this field disables access to the remote I2C Serializer.
0 RSVD R/W 0 Reserved.
0x08 Slave ID[0] 7:1 Slave ID0 R/W 0x00'h 7-bit Remote Slave Device ID 0 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID0, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0 RSVD R/W 0 Reserved.
0x09 Slave ID[1] 7:1 Slave ID1 R/W 0x00'h 7-bit Remote Slave Device ID 1 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID1, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0 RSVD R/W 0 Reserved.
0x0A Slave ID[2] 7:1 Slave ID2 R/W 0x00'h 7-bit Remote Slave Device ID 2 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID2, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0 RSVD R/W 0 Reserved.
0x0B Slave ID[3] 7:1 Slave ID3 R/W 0x00'h 7-bit Remote Slave Device ID 3 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID3, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0 RSVD R/W 0 Reserved.
0x0C Slave ID[4] 7:1 Slave ID4 R/W 0x00'h 7-bit Remote Slave Device ID 4 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID4, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0 RSVD R/W 0 Reserved.
0x0D Slave ID[5] 7:1 Slave ID5 R/W 0x00'h 7-bit Remote Slave Device ID 5 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID5 , the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0 RSVD R/W 0 Reserved.
0x0E Slave ID[6] 7:1 Slave ID6 R/W 0x00'h 7-bit Remote Slave Device ID 6 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID6, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0 RSVD R/W 0 Reserved.
0x0F Slave ID[7] 7:1 Slave ID7 R/W 0x00'h 7-bit Remote Slave Device ID 7 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID7, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0 RSVD R/W 0 Reserved.
0x10 Slave Alias[0] 7:1 Slave Alias ID0 R/W 0x00'h 7-bit Remote Slave Device Alias ID 0 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID0 register. A value of 0 in this field disables access to the remote I2C Slave.
0 RSVD R/W 0 Reserved.
0x11 Slave Alias[1] 7:1 Slave Alias ID1 R/W 0x00'h 7-bit Remote Slave Device Alias ID 1 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID1 register. A value of 0 in this field disables access to the remote I2C Slave.
0 RSVD R/W 0 Reserved.
0x12 Slave Alias[2] 7:1 Slave Alias ID2 R/W 0x00'h 7-bit Remote Slave Device Alias ID 2 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID2 register. A value of 0 in this field disables access to the remote I2C Slave.
0 RSVD R/W 0 Reserved.
0x13 Slave Alias[3] 7:1 Slave Alias ID3 R/W 0x00'h 7-bit Remote Slave Device Alias ID 3 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID3 register. A value of 0 in this field disables access to the remote I2C Slave.
0 RSVD R/W 0 Reserved.
0x14 Slave Alias[4] 7:1 Slave Alias ID4 R/W 0x00'h 7-bit Remote Slave Device Alias ID 4 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID4 register. A value of 0 in this field disables access to the remote I2C Slave.
0 RSVD R/W 0 Reserved.
0x15 Slave Alias[5] 7:1 Slave Alias ID5 R/W 0x00'h 7-bit Remote Slave Device Alias ID 5 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID5 register. A value of 0 in this field disables access to the remote I2C Slave.
0 RSVD R/W 0 Reserved.
0x16 Slave Alias[6] 7:1 Slave Alias ID6 R/W 0x00'h 7-bit Remote Slave Device Alias ID 6 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID6 register. A value of 0 in this field disables access to the remote I2C Slave.
0 RSVD R/W 0 Reserved.
0x17 Slave Alias[7] 7:1 Slave Alias ID7 R/W 0x00'h 7-bit Remote Slave Device Alias ID 7 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID7 register. A value of 0 in this field disables access to the remote I2C Slave.
0 RSVD R/W 0 Reserved.
0x18 Parity Errors Threshold 7:0 Parity Error Threshold Byte 0 R/W 0x00'h Parity errors threshold on the Forward channel during normal information. This sets the maximum number of parity errors that can be counted using register 0x1A.
Least significant Byte.
0x19 Parity Errors Threshold 7:0 Parity Error Threshold Byte 1 R/W 0x01'h Parity errors threshold on the Forward channel during normal operation. This sets the maximum number of parity errors that can be counted using register 0x1B.
Most significant Byte.
0x1A Parity Errors 7:0 Parity Error Byte 0 R 0x00'h Number of parity errors in the Forward channel during normal operation.
Least significant Byte.
0x1B Parity Errors 7:0 Parity Error Byte 1 R 0x00'h Number of parity errors in the Forward channel during normal operation.
Most significant Byte.
0x1C General Status 7:4 Rev-ID R 0x0'h Revision ID.
0x0: Production Revision ID.
3 RSVD R 0 Reserved.
2 Parity Error R 0 Parity Error detected.
1: Parity Errors detected.
0: No Parity Errors.
1 Signal Detect R 0 1: Serial input detected.
0: Serial input not detected.
0 Lock R 0 De-Serializer CDR, PLL's clock to recovered clock frequency.
1: De-Serializer locked to recovered clock.
0: De-Serializer not locked.
0x1D GPIO[1] and GPIO[0] Config 7 GPIO1 Output Value R/W 0 Local GPIO Output Value This value is the output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output.
6 RSVD R/W 0 Reserved.
5 GPIO1 Direction R/W 1 Local GPIO Direction.
1: Input.
0: Output.
4 GPIO1 Enable R/W 1 GPIO Function Enable.
1: Enable GPIO forwarding to the serializer
0: Enable local GPIO operation
3 GPIO0 Output Value R/W 0 Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output.
2 RSVD R/W 0 Reserved.
1 GPIO0 Direction R/W 1 Local GPIO Direction.
1: Input.
0: Output.
0 GPIO0 Enable R/W 1 GPIO Function Enable.
1: Enable GPIO forwarding to the serializer
0: Enable local GPIO operation
0x1E GPIO[3] and GPIO[2] Config 7 GPIO3 Output Value R/W 0 Local GPIO Output Value This value is the output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output.
6 RSVD R/W 0 Reserved.
5 GPIO3 Direction R/W 1 Local GPIO Direction.
1: Input.
0: Output.
4 GPIO3 Enable R/W 1 GPIO Function Enable.
1: Enable GPIO forwarding to the serializer
0: Enable local GPIO operation
3 GPIO2 Output Value R/W 0 Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output.
2 RSVD R/W 0 Reserved.
1 GPIO2 Direction R/W 1 Local GPIO Direction.
1: Input.
0: Output.
0 GPIO2 Enable R/W 1 GPIO Function Enable.
1: Enable GPIO forwarding to the serializer
0: Enable local GPIO operation
0x1F Mode and OSS Select 7 OEN_OSS Override R/W 0 Allows overriding OEN and OSS select coming from Pins.
1: Overrides OEN/OSS_SEL selected by pins.
0: Does NOT override OEN/OSS_SEL select by pins.
6 OEN Select R/W 0 OEN configuration from register.
5 OSS Select R/W 0 OSS_SEL configuration from register.
4 MODE_OVERRIDE R/W 0 Allows overriding mode select bits coming from forward-channel.
1: Overrides MODE select bits.
0: Does not override MODE select bits.
3 PIN_MODE_12–bit HF mode R 0 Status of mode select pin.
2 PIN_MODE_10-bit mode R 0 Status of mode select pin.
1 MODE_12–bit High Frequency R/W 0 Selects 12-bit high frequency mode. This bit is automatically updated by the mode settings from MODE pin unless MODE_OVERRIDE is SET.
1: 12-bit high frequency mode is selected.
0: 12-bit high frequency mode is not selected.
To select 12-bit low frequency mode by register override, set 0x1F[1] = 0x1F[0] = 0
0 MODE_10–bit mode R/W 0 Selects 10-bit mode. This bit is automatically updated by the mode settings from MODE pin unless MODE_OVERRIDE is SET.
1: Enables 10-bit mode.
0: Disables 10-bit mode.
0x20 BCC Watchdog Control 7:1 BCC Watchdog timer R/W 0x7F'h
(111_1111'b)		 The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2ms. This field should not be set to 0.
0 BCC Watchdog Timer Disable R/W 0 Disable Bidirectional Control Channel Watchdog Timer.
1: Disables BCC Watchdog Timer operation.
0: Enables BCC Watchdog Timer operation.
0x21 I2C Control 1 7 I2C Pass-Through All R/W 0 1: Enable Forward Control Channel pass-through of all I2C accesses to I2C IDs that do not match the Deserializer I2C ID. The I2C accesses are then remapped to address specified in register 0x06 (SER ID).
0: Enable Forward Control Channel pass-through only of I2C accesses to I2C IDs matching either the remote Serializer ID or the remote I2C IDs.
6:4 I2C SDA Hold Time R/W 0x1'h Internal SDA Hold Time This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50ns.
3:0 I2C Filter Depth R/W 0x7'h I2C Glitch Filter Depth This field configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 10ns.
0x22 I2C Control 2 7 Forward Channel Sequence Error R 0 Control Channel Sequence Error Detected This bit indicates a sequence error has been detected in forward control channel.
1: If this bit is set, an error may have occurred in the control channel operation.
0: No forward channel errors have been detected on the control channel.
6 Clear Sequence Error R/W 0 1: Clears the Sequence Error Detect bit.
0: No effect.
5 RSVD R 0 Reserved.
4:3 SDA Output Delay R/W 00 SDA Output Delay This field configures output delay on the SDA output. Setting this value will increase output delay in units of 50ns. Nominal output delay values for SCL to SDA are:
00 : ~350 ns
01: ~400 ns
10: ~450 ns
11: ~500 ns
2 Local Write Disable R/W 0 Disable Remote Writes to local registers Setting this bit to a 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Deserializer registers from an I2C master attached to the Serializer. Setting this bit does not affect remote access to I2C slaves at the Deserializer.
1 I2C Bus Timer Speedup R/W 0 Speed up I2C Bus Watchdog Timer.
1: Watchdog Timer expires after approximately 50 µs.
0: Watchdog Timer expires after approximately 1 s.
0 I2C Bus Timer Disable R/W 0 Disable I2C Bus Watchdog Timer When the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1 second, the I2C bus will assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL.
0x23 General Purpose Control 7:0 GPCR R/W 0x00'h Scratch Register.
0x24 BIST Control 7:4 RSVD R/W 0x0 Reserved.
3 BIST Pin Configuration R/W 1 Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through register bit "reg_24[0]".
2:1 BIST Clock Source R/W 00 BIST Clock Source.
See Table 5
0 BIST Enable R/W 0 BIST Control.
1: Enabled.
0: Disabled.
0x25 Parity Error Count 7:0 BIST Error Count R 0x00'h Number of Forward Channel Parity errors in BIST mode.
0x26 Bidirectional Control Channel (BCC) Tuning for Channel 0 (RIN0±) 7:6 RSVD R/W 00 Reserved.
5:4 RSVD R/W 00 Reserved.
3:2 Termination Resistance Control R/W 00 00: 50 Ω (default)
01: 47.4 Ω
10: 45.3 Ω
11: 37.7 Ω
1:0 RSVD R/W 00 Reserved.
0x27 Forward Channel Tuning for Channel 0 (RIN0±) 7:0 Impedance Control R/W 0x00 0x00: Default
0x70: Beneficial for longer cable (> 6 meter) applications that have system impedance mismatch on deserializer side.
0x28 -
0x3B		 Reserved.
0x3C Oscillator output divider select 7:2 RSVD R/W 0x00 Reserved.
1:0 OSC OUT DIVIDER SEL R/W 00 Selects the divider for the OSC clock out on PCLK when system is not locked and selected by OEN/OSS_SEL 0x02[5]:
00: 50 M (±30%)
01: 25 M (±30%)
1X: 12.5 M (±30%)
0x3D -
0x3E		 Reserved.
0x3F CML Output Enable 7:5 RSVD R/W 0x0 Reserved.
4 CML OUT Enable R/W 1 CML Output Driver Enable is Active-Low.
0: CML Loop-through Driver is powered up.
1: CML Loop-through Driver is powered down.
3:0 RSVD R/W 0x0 Reserved.
0x40 SCL High Time 7:0 SCL High Time R/W 0x82'h
(1000_0010'b)		 I2C Master SCL High Time This field configures the high pulse width of the SCL output when the De-Serializer is the Master on the local I2C bus. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum (4 μs + 0.3 μs of rise time for cases where rise time is very fast) SCL high time with the internal oscillator clock running at 26 MHz rather than the nominal 20 MHz.
0x41 SCL Low Time 7:0 SCL Low Time R/W 0x82'h
(1000_0010'b)		 I2C SCL Low Time This field configures the low pulse width of the SCL output when the De-Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum (4.7 µs + 0.3 µs of fall time for cases where fall time is very fast) SCL low time with the internal oscillator clock running at 26 MHz rather than the nominal 20 MHz.
0x42 CRC Force Error 7:2 RSVD R/W 0x00 Reserved.
1 Force Back Channel Error R/W 0 1: This bit introduces multiple errors into Back channel frame.
0: No effect.
0 Force One Back Channel Error R/W 0 1: This bit introduces ONLY one error into Back channel frame. Self clearing bit.
0: No effect.
0x43 -
0x45		 Reserved.
0x46 Bidirectional Control Channel (BCC) Tuning for Channel 1 (RIN1±) 7:6 RSVD R/W 00 Reserved.
5:4 RSVD R/W 00 Reserved.
3:2 Termination Resistance Control R/W 00 00: 50 Ω (default)
01: 47.4 Ω
10: 45.3 Ω
11: 37.7 Ω
1:0 RSVD R/W 00 Reserved.
0x47 Forward Channel Tuning for Channel 1 (RIN1±) 7:0 Impedance Control R/W 0x00 0x00: Default
0x70: Beneficial for longer cable (> 6 meter) applications that have system impedance mismatch on deserializer side.
0x48 -
0x4B		 Reserved.
0x4C SEL Register 7 Pin Channel SEL Override R/W 0 0: SEL pin selects the FPD-III serial input
1: 0x4C[6] selects the FPD-III serial input
6 Channel SEL R/W 0 0: Channel 0 is selected
1: Channel 1 is selected
5:0 RSVD R/W 0x00 Reserved.
0x4D AEQ Test Mode Select 7 RSVD R/W 0 Reserved.
6 AEQ Bypass R/W 0 Bypass AEQ and use set manual EQ value using register 0x04.
5:0 RSVD R/W 0x20 Reserved.
0x4E EQ Value 7:4 AEQ / Manual Eq Readback R 0000 Read back the adaptive and manual EQ level. EQ gain values listed below are @ maximum line rate (1.4 Gbps).
0000 = ~16.5 dB (minimum)
0001 = ~19.0 dB
0011 = ~20.5 dB
0111 = ~22.0 dB
1111 = ~23.0 dB (maximum)
3:0 RSVD R 0x0 Reserved.