ZHCSU80 December   2023 CC2340R2

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 功能方框图
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram – RGE Package (Top View)
    2. 6.2 Signal Descriptions – RGE Package
    3. 6.3 Connections for Unused Pins and Modules – RGE Package
    4. 6.4 RGE Peripheral Pin Mapping
    5. 6.5 RGE Peripheral Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  DCDC
    5. 7.5  Global LDO (GLDO)
    6. 7.6  Power Supply and Modules
    7. 7.7  Battery Monitor
    8. 7.8  Temperature Sensor
    9. 7.9  Power Consumption - Power Modes
    10. 7.10 Power Consumption - Radio Modes
    11. 7.11 Nonvolatile (Flash) Memory Characteristics
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 RF Frequency Bands
    14. 7.14 Bluetooth Low Energy - Receive (RX)
    15. 7.15 Bluetooth Low Energy - Transmit (TX)
    16. 7.16 2.4 GHz RX/TX CW
    17. 7.17 Timing and Switching Characteristics
      1. 7.17.1 Reset Timing
      2. 7.17.2 Wakeup Timing
      3. 7.17.3 Clock Specifications
        1. 7.17.3.1 48 MHz Crystal Oscillator (HFXT)
        2. 7.17.3.2 48 MHz RC Oscillator (HFOSC)
        3. 7.17.3.3 32 kHz Crystal Oscillator (LFXT)
        4. 7.17.3.4 32 kHz RC Oscillator (LFOSC)
    18. 7.18 Peripheral Characteristics
      1. 7.18.1 UART
        1. 7.18.1.1 UART Characteristics
      2. 7.18.2 SPI
        1. 7.18.2.1 SPI Characteristics
        2. 7.18.2.2 SPI Controller Mode
        3. 7.18.2.3 SPI Timing Diagrams - Controller Mode
        4. 7.18.2.4 SPI Peripheral Mode
        5. 7.18.2.5 SPI Timing Diagrams - Peripheral Mode
      3. 7.18.3 I2C
        1. 7.18.3.1 I2C
        2. 7.18.3.2 I2C Timing Diagram
      4. 7.18.4 GPIO
        1. 7.18.4.1 GPIO DC Characteristics
      5. 7.18.5 ADC
        1. 7.18.5.1 Analog-to-Digital Converter (ADC) Characteristics
      6. 7.18.6 Comparators
        1. 7.18.6.1 Ultra-low power comparator
    19. 7.19 Typical Characteristics
      1. 7.19.1 MCU Current
      2. 7.19.2 RX Current
      3. 7.19.3 TX Current
      4. 7.19.4 RX Performance
      5. 7.19.5 TX Performance
      6. 7.19.6 ADC Performance
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  System CPU
    3. 8.3  Radio (RF Core)
      1. 8.3.1 Bluetooth 5.3 Low Energy
    4. 8.4  Memory
    5. 8.5  Cryptography
    6. 8.6  Timers
    7. 8.7  Serial Peripherals and I/O
    8. 8.8  Battery and Temperature Monitor
    9. 8.9  µDMA
    10. 8.10 Debug
    11. 8.11 Power Management
    12. 8.12 Clock Systems
    13. 8.13 Network Processor
  10. 9 Application, Implementation, and Layout
    1. 9.1 Reference Designs
    2. 9.2 Junction Temperature Calculation
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
      1. 10.2.1 SimpleLink™ Microcontroller Platform
    3. 10.3 Documentation Support
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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7.11 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Flash sector size 2 KB
Supported flash erase cycles before failure, full bank(1)(2) 30 k Cycles
Supported flash erase cycles before failure, single sector(3) 60 k Cycles
Maximum number of write operations per row before sector erase(4) 83 Write Operations
Flash retention 105 °C 11.4 Years
Flash retention 125 °C 10 Years
Flash sector erase current Average delta current 1.2 mA
Flash sector erase time(5) 0 erase cycles 2.2 ms
Flash write current Average delta current, full sector at a time 1.7 mA
Flash write time(5) full sector (2kB) at a time, 0 erase cycles 8.3 ms
(1) A full bank erase is counted as a single erase cycle on each sector
(2) Aborting flash during erase or program modes is not a safe operation.
(3) Up to 16 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k cycles
(4) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number of write operations per row is reached.
(5) This number is dependent on Flash aging and increases over time and erase cycles