ZHCSAF0E September   2012  – January 2018

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
    1.     典型应用电路
  4. 修订历史记录
  5. 说明 (续)
  6. Device Comparisons
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Operational Flow Chart
    4. 9.4 Feature Description
      1. 9.4.1 Input Voltage Protection
        1. 9.4.1.1 Input Overvoltage Protection
        2. 9.4.1.2 Bad Adaptor Detection/Rejection
        3. 9.4.1.3 Sleep Mode
        4. 9.4.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)
      2. 9.4.2 Battery Protection
        1. 9.4.2.1 Output Overvoltage Protection
        2. 9.4.2.2 Battery Detection at Power Up in DEFAULT Mode
        3. 9.4.2.3 Battery Short Protection
        4. 9.4.2.4 Battery Detection in Host Mode
      3. 9.4.3 DEFAULT Mode
      4. 9.4.4 USB Friendly Power Up
      5. 9.4.5 Input Current Limiting At Power Up
    5. 9.5 Device Functional Modes
      1. 9.5.1 Charge Mode Operation
        1. 9.5.1.1 Charge Profile
      2. 9.5.2 PWM Controller in Charge Mode
      3. 9.5.3 Battery Charging Process
      4. 9.5.4 Thermal Regulation and Protection
      5. 9.5.5 Charge Status Output, STAT Pin
      6. 9.5.6 Control Bits in Charge Mode
        1. 9.5.6.1 CE Bit (Charge Mode)
        2. 9.5.6.2 RESET Bit
        3. 9.5.6.3 OPA_Mode Bit
      7. 9.5.7 Control Pins in Charge Mode
        1. 9.5.7.1 CD Pin (Charge Disable)
      8. 9.5.8 BOOST Mode Operation
        1. 9.5.8.1 PWM Controller in Boost Mode
        2. 9.5.8.2 Boost Start Up
        3. 9.5.8.3 PFM Mode at Light Load
        4. 9.5.8.4 Protection in Boost Mode
          1. 9.5.8.4.1 Output Overvoltage Protection
          2. 9.5.8.4.2 Output Overload Protection
          3. 9.5.8.4.3 Battery Overvoltage Protection
        5. 9.5.8.5 STAT Pin in Boost Mode
      9. 9.5.9 High Impedance (Hi-Z) Mode
    6. 9.6 Programming
      1. 9.6.1 Serial Interface Description
        1. 9.6.1.1 F/S Mode Protocol
        2. 9.6.1.2 H/S Mode Protocol
        3. 9.6.1.3 I2C Update Sequence
        4. 9.6.1.4 Slave Address Byte
        5. 9.6.1.5 Register Address Byte
    7. 9.7 Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Application
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
      2. 10.1.2 Charge Current Sensing Resistor Selection Guidelines
      3. 10.1.3 Output Inductor and Capacitance Selection Guidelines
    2. 10.2 Typical Performance Curves
  11. 11Power Supply Recommendations
    1. 11.1 System Load After Sensing Resistor
      1. 11.1.1 The Advantages:
      2. 11.1.2 Design Requirements and Potential Issues:
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 接收文档更新通知
    3. 13.3 Community Resources
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息
    1. 14.1 封装概要
      1. 14.1.1 芯片级封装尺寸

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Register Description

Table 3. Status/Control Register (Read/Write)
Memory Location: 00, Reset State: x1xx 0xxx

BITNAMEREAD/WRITEFUNCTION
B7 (MSB) TMR_RST/OTG Read/Write Write: TMR_RST function, write "1" to reset the safety timer (auto clear)
Read: OTG pin status, 0-OTG pin at Low level, 1-OTG pin at High level
B6 EN_STAT Read/Write 0-Disable STAT pin function, 1-Enable STAT pin function (default 1)
B5 STAT2 Read Only 00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault
B4 STAT1 Read Only
B3 BOOST Read Only 1-Boost mode, 0-Not in boost mode
B2 FAULT_3 Read Only Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Bad Adaptor or VBUS<VUVLO,
100-Output OVP, 101-Thermal shutdown, 110-Timer fault, 111-No battery
Boost mode: 000-Normal, 001-VBUS OVP, 010-Over load, 011-Battery voltage is too low, 100-Battery OVP, 101-Thermal shutdown, 110-Timer fault, 111-NA
B1 FAULT_2 Read Only
B0 (LSB) FAULT_1 Read Only

Table 4. Control Register (Read/Write)
Memory Location: 01, Reset State: 0011 0000

BITNAMEREAD/WRITEFUNCTION
B7 (MSB) Iin_Limit_2 Read/Write 00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit, 10-USB host/charger with 800-mA current limit, 11-No input current limit
B6 Iin_Limit_1 Read/Write
B5 V(LOWV_2)(1) Read/Write Weak battery voltage threshold: 200mV step (default 1)
B4 V(LOWV_1)(1) Read/Write Weak battery voltage threshold: 100mV step (default 1)
B3 TE Read/Write 1-Enable charge current termination, 0-Disable charge current termination (default 0)
B2 CE Read/Write 1-Charger is disabled, 0-Charger enabled (default 0)
B1 HZ_MODE Read/Write 1-High impedance mode, 0-Not high impedance mode (default 0)
B0 (LSB) OPA_MODE Read/Write 1-Boost mode, 0-Charger mode (default 0)
The range of the weak battery voltage threshold (V(LOWV)) is 3.4 V to 3.7 V with an offset of 3.4 V and steps of 100 mV (default 3.7 V, using bits B4-B5).

Table 5. Control/Battery Voltage Register (Read/Write)
Memory Location: 02, Reset State: 0000 1010

BITNAMEREAD/WRITEFUNCTION
B7 (MSB) VO(REG5) Read/Write Battery Regulation Voltage: 640 mV step (default 0)
B6 VO(REG4) Read/Write Battery Regulation Voltage: 320 mV step (default 0)
B5 VO(REG3) Read/Write Battery Regulation Voltage: 160 mV step (default 0)
B4 VO(REG2) Read/Write Battery Regulation Voltage: 80 mV step (default 0)
B3 VO(REG1) Read/Write Battery Regulation Voltage: 40 mV step (default 1)
B2 VO(REG0) Read/Write Battery Regulation Voltage: 20 mV step (default 0)
B1 OTG_PL Read/Write 1-OTG Boost Enable with High level, 0-OTG Boost Enable with Low level (default 1); not applicable to OTG pin control of current limit at POR in default mode
B0 (LSB) OTG_EN Read/Write 1-Enable OTG Pin in HOST mode, 0-Disable OTG pin in HOST mode (default 0), not applicable to OTG pin control of current limit at POR in default mode
  • Charge voltage range is 3.5 V to 4.44 V with the offset of 3.5 V and steps of 20 mV (default 3.54 V), using bits B2-B7.

Table 6. Vender/Part/Revision Register (Read only)
Memory Location: 03, Reset State: 0101 000x

BITNAMEREAD/WRITEFUNCTION
B7 (MSB) Vender2 Read Only Vender Code: bit 2 (default 0)
B6 Vender1 Read Only Vender Code: bit 1 (default 1)
B5 Vender0 Read Only Vender Code: bit 0 (default 0)
B4 PN1 Read Only For I2C Address 6AH: 01–NA, 10–bq24157, 11–NA.
B3 PN0 Read Only
B2 Revision2 Read Only 011: Revision 1.0;
001: Revision 1.1;
100-111: Future Revisions
B1 Revision1 Read Only
B0 (LSB) Revision0 Read Only

Table 7. Battery Termination/Fast Charge Current Register (Read/Write)
Memory Location: 04, Reset State: 0000 0001

BITNAMEREAD/WRITEFUNCTION
B7 (MSB) Reset Read/Write Write: 1-Charger in reset mode, 0-No effect, Read: always get "0"
B6 VI(CHRG3)(1) Read/Write Charge current sense voltage: 27.2 mV step
B5 VI(CHRG2)(1) Read/Write Charge current sense voltage: 13.6 mV step
B4 VI(CHRG1)(1) Read/Write Charge current sense voltage: 6.8 mV step
B3 VI(CHRG0)(1) Read/Write NA
B2 VI(TERM2)(2) Read/Write Termination current sense voltage: 13.6 mV step (default 0)
B1 VI(TERM1)(2) Read/Write Termination current sense voltage: 6.8 mV step (default 0)
B0 (LSB) VI(TERM0)(2) Read/Write Termination current sense voltage: 3.4 mV step (default 1)
See Table 12
See Table 11
  • Charge current sense voltage offset is 37.4 mV and default charge current is 550 mA, if 68-mΩ sensing resistor is used and LOW_CHG=0.

Table 8. Special Charger Voltage/Enable Pin Status Register
Memory location: 05, Reset state: 000X X100

BITNAMEREAD/WRITEFUNCTION
B7 (MSB) NA Read/Write NA
B6 NA Read/Write NA
B5 LOW_CHG Read/Write 0 – Normal charge current sense voltage at 04H (default 1),
1 – Low charge current sense voltage of 22.1 mV
B4 DPM_STATUS Read Only 0 – DPM mode is not active,
1 – DPM mode is active
B3 CD_STATUS Read Only 0 – CD pin at LOW level,
1 – CD pin at HIGH level
B2 VSREG2 Read/Write Special charger voltage: 320 mV step (default 1)
B1 VSREG1 Read/Write Special charger voltage: 160 mV step (default 0)
B0 (LSB) VSREG0 Read/Write Special charger voltage: 80 mV step (default 0)

  • Special charger voltage offset is 4.2 V and default special charger voltage is 4.52 V.
  • Maximum charge current sense voltage offset is 37.4 mV (550 mA), default at 64.6 mV (950 mA) and the maximum charge current option is 1.55 A (105.4 mV), if 55-mΩ sensing resistor is used.
  • Maximum battery regulation voltage offset is 4.2V (default at 4.2 V) and maximum battery regulation voltage option is 4.44V.
  • Memory location 06H resets only when V(CSOUT) drops below either 1) V(SHORT) threshold (typ. 2.05 V) if VBUS > V(UVLO) or 2) the digital reset threshold of 2.4 V typical if VBUS < V(UVLO). Programmed values in the safety limit register exclude higher values from memory locations 02 (battery regulation voltage), and from memory location 04 (fast charge current) from being successfully written.
  • If host accesses (write command) to some other register before Safety limit register, the safety default values are used.