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Number of outputs 4 Output type LP-HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 328.125 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type Differential, LVCMOS, XTAL Operating temperature range (°C) -40 to 105 TI functional safety category Functional Safety-Capable Features Integrated EEPROM, Pin programmable, Serial interface Rating Automotive
Number of outputs 4 Output type LP-HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 328.125 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type Differential, LVCMOS, XTAL Operating temperature range (°C) -40 to 105 TI functional safety category Functional Safety-Capable Features Integrated EEPROM, Pin programmable, Serial interface Rating Automotive
VQFN (RGE) 24 16 mm² (4 mm × 4 mm)
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 2: –40°C to 105°C
  • Functional Safety-Capable
  • Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12kHz – 20MHz, Fout > 100MHz) as:
    • Integer mode:
      • Differential output: 350fs typical (typ.), 600fs (max.)
      • LVCMOS output: 1.05ps (typ.), 1.5ps (max.)
    • Fractional mode:
      • Differential output: 1.7ps (typ.), 2.1ps (max.)
      • LVCMOS output: 2.0ps (typ.), 4.0ps (max.)
  • Supports PCIe Gen 1, 2, and 3 with SSC and Gen 1, 2, 3, 4, 5, 6, and 7 without SSC
  • Typical power consumption: 65mA for 4-output channel, 23mA for 1-output channel
  • Universal clock input
    • Differential AC-coupled or LVCMOS: 10MHz to 200MHz
    • Crystal: 10MHz to 50MHz
  • Flexible output clock distribution
    • Four channel dividers: Up to five unique output frequencies from 24kHz to 328.125MHz
    • Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
    • Glitchless output divider switching and output channel synchronization
    • Individual output enable through GPIO and register
  • Frequency margining options
    • DCO mode: frequency increment/decrement with 10ppb or less step-size
  • Fully-integrated, configurable loop bandwidth: 100kHz to 1.6MHz
  • Single or mixed supply for level translation: 1.8V, 2.5V, 3.3V
  • Configurable GPIOs and flexible configuration options
    • I2C-compatible interface: up to 400kHz
    • Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
  • Supports 100Ω systems
  • Low electromagnetic emissions
  • Small footprint: 24-pin VQFN (4mm × 4mm)
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 2: –40°C to 105°C
  • Functional Safety-Capable
  • Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12kHz – 20MHz, Fout > 100MHz) as:
    • Integer mode:
      • Differential output: 350fs typical (typ.), 600fs (max.)
      • LVCMOS output: 1.05ps (typ.), 1.5ps (max.)
    • Fractional mode:
      • Differential output: 1.7ps (typ.), 2.1ps (max.)
      • LVCMOS output: 2.0ps (typ.), 4.0ps (max.)
  • Supports PCIe Gen 1, 2, and 3 with SSC and Gen 1, 2, 3, 4, 5, 6, and 7 without SSC
  • Typical power consumption: 65mA for 4-output channel, 23mA for 1-output channel
  • Universal clock input
    • Differential AC-coupled or LVCMOS: 10MHz to 200MHz
    • Crystal: 10MHz to 50MHz
  • Flexible output clock distribution
    • Four channel dividers: Up to five unique output frequencies from 24kHz to 328.125MHz
    • Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
    • Glitchless output divider switching and output channel synchronization
    • Individual output enable through GPIO and register
  • Frequency margining options
    • DCO mode: frequency increment/decrement with 10ppb or less step-size
  • Fully-integrated, configurable loop bandwidth: 100kHz to 1.6MHz
  • Single or mixed supply for level translation: 1.8V, 2.5V, 3.3V
  • Configurable GPIOs and flexible configuration options
    • I2C-compatible interface: up to 400kHz
    • Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
  • Supports 100Ω systems
  • Low electromagnetic emissions
  • Small footprint: 24-pin VQFN (4mm × 4mm)

The CDCE6214-Q1 is a 4-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source can be a single-ended or differential input clock source, or a crystal. The CDCE6214-Q1 features a frac-N PLL to synthesize unrelated base frequency from any input frequency.

The CDCE6214-Q1 can be configured through the I2C interface in fall-back mode only. In the absence of the serial interface, the GPIO pins can be used in pin mode to configure the product into distinctive configurations.

On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.

Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8V, 2.5V, or 3.3V ±5% supply, and output blocks operate from a 1.8V, 2.5V, or 3.3V ±5% supply.

The CDCE6214-Q1 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214-Q1 an easy-to-use, instant on clocking device with a low power consumption.

The CDCE6214-Q1 is a 4-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source can be a single-ended or differential input clock source, or a crystal. The CDCE6214-Q1 features a frac-N PLL to synthesize unrelated base frequency from any input frequency.

The CDCE6214-Q1 can be configured through the I2C interface in fall-back mode only. In the absence of the serial interface, the GPIO pins can be used in pin mode to configure the product into distinctive configurations.

On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.

Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8V, 2.5V, or 3.3V ±5% supply, and output blocks operate from a 1.8V, 2.5V, or 3.3V ±5% supply.

The CDCE6214-Q1 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214-Q1 an easy-to-use, instant on clocking device with a low power consumption.

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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 CDCE6214-Q1 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM 数据表 (Rev. D) PDF | HTML 2026-11-4
应用手册 PCIe 应用的时钟 PDF | HTML 英语版 PDF | HTML 2023-11-29
功能安全信息 CDCE6214-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA PDF | HTML 2021-4-15
技术文章 Optimizing eAVB for automotive applications using clock generators PDF | HTML 2020-5-8
证书 CDCE6214-Q1EVM Declaration of Conformity (DoC) 2020-4-28
应用手册 Frequency Margining and eAVB System Design With CDCE6214-Q1 PDF | HTML 2020-4-2
应用手册 CDCE6214-Q1 Crystal-Based Oscillator Design 2019-12-9
用户指南 CDCE6214-Q1 Registers (Rev. B) 2019-11-27

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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

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仿真模型

CDCE6214-Q1 IBIS Model

SNAM233.ZIP (251 KB) - IBIS 模型
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封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RGE) 24 Ultra Librarian

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