产品详细信息

DSP 1 C64x DSP MHz (Max) 600 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (C) -40 to 105, 0 to 90
DSP 1 C64x DSP MHz (Max) 600 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (C) -40 to 105, 0 to 90
FCBGA (GTS) 288 529 mm² 23 x 23 FCBGA (ZTS) 288 529 mm² 23 x 23
  • High-Performance Fixed-Point Digital Signal Processor (TMS320C6418)
    • Commercial Temperature Device
      • 1.67-ns Instruction Cycle Time
      • 600-MHz Clock Rate
      • 4800 MIPS
    • Extended Temperature Device
      • 2-ns Instruction Cycle Time
      • 500-MHz Clock Rate
      • 4000 MIPS
    • Eight 32-Bit Instructions/Cycle
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
  • Viterbi Decoder Coprocessor (VCP)
    • Supports Over 500 7.95-Kbps AMR
    • Programmable Code Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 4M-Bit (512K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each
  • Two Inter-Integrated Circuit (I2C) Buses
    • Additional GPIO Capability
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • On-Chip Fundamental Oscillator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 288-Pin Ball Grid Array (BGA) Package (GTS and ZTS Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.4-V Internal (-600)
  • 3.3-V I/Os, 1.2-V Internal (A-500)

VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.

  • High-Performance Fixed-Point Digital Signal Processor (TMS320C6418)
    • Commercial Temperature Device
      • 1.67-ns Instruction Cycle Time
      • 600-MHz Clock Rate
      • 4800 MIPS
    • Extended Temperature Device
      • 2-ns Instruction Cycle Time
      • 500-MHz Clock Rate
      • 4000 MIPS
    • Eight 32-Bit Instructions/Cycle
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
  • Viterbi Decoder Coprocessor (VCP)
    • Supports Over 500 7.95-Kbps AMR
    • Programmable Code Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 4M-Bit (512K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each
  • Two Inter-Integrated Circuit (I2C) Buses
    • Additional GPIO Capability
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • On-Chip Fundamental Oscillator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 288-Pin Ball Grid Array (BGA) Package (GTS and ZTS Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.4-V Internal (-600)
  • 3.3-V I/Os, 1.2-V Internal (A-500)

VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.

The TMS320C64x™ DSPs (including the TMS320C6418 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6418 (C6418) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI). The high-performance, lower-cost C6418 DSP enables customers to reduce system costs for telecom, software radio, Digital Terrestrial Television Broadcasting (DTTB), and digital Broadcast Satellite/Communication Satellite (BS/CS) applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6418 device offers cost-effective solutions to high-performance DSP programming challenges. The C6418 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The C6418 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6418 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6418 device has a high-performance embedded coprocessor [Viterbi Decoder Coprocessor (VCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. Communications between the VCP and the CPU are carried out through the EDMA controller.

The C6418 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 4-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache (up to 256K bytes), or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6418 has sufficient bandwidth to support all six serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The I2C ports on the TMS320C6418 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6418 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C64x™ DSPs (including the TMS320C6418 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6418 (C6418) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI). The high-performance, lower-cost C6418 DSP enables customers to reduce system costs for telecom, software radio, Digital Terrestrial Television Broadcasting (DTTB), and digital Broadcast Satellite/Communication Satellite (BS/CS) applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6418 device offers cost-effective solutions to high-performance DSP programming challenges. The C6418 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The C6418 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6418 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6418 device has a high-performance embedded coprocessor [Viterbi Decoder Coprocessor (VCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. Communications between the VCP and the CPU are carried out through the EDMA controller.

The C6418 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 4-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache (up to 256K bytes), or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6418 has sufficient bandwidth to support all six serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The I2C ports on the TMS320C6418 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6418 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

下载

No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

技术文档

star = TI 精选相关文档
未找到结果。请清除搜索,并重试。
显示全部 66 项
类型 标题 下载最新的英文版本 日期
* 数据表 TMS320C6418 Fixed-Point Digital Signal Processor 数据表 (Rev. D) 2006年 1月 17日
* 勘误表 TMS320C6418 Digital Signal Processor Silicon Errata (Rev. A) 2004年 11月 24日
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 下载英文版本 (Rev.A) 2021年 5月 19日
技术文章 Bringing the next evolution of machine learning to the edge 2018年 11月 27日
技术文章 How quality assurance on the Processor SDK can improve software scalability 2018年 8月 22日
技术文章 Clove: Low-Power video solutions based on Sitara™ AM57x processors 2016年 7月 21日
技术文章 Spring has sprung. A sale has sprung. 2016年 4月 4日
用户指南 Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012年 8月 9日
应用手册 Power Consumption Guide for the C66x 2011年 10月 6日
用户指南 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010年 7月 30日
用户指南 TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009年 7月 2日
用户指南 TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (Rev. J) 2008年 11月 20日
应用手册 TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 2007年 9月 4日
应用手册 Thermal Considerations Application Report 2007年 5月 20日
用户指南 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 2007年 4月 11日
更多文献资料 TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007年 4月 4日
用户指南 TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 2007年 3月 26日
用户指南 TMS320C6000 DSP Multichannel Buffered Serial Port ( McBSP) Reference Guide (Rev. G) 2006年 12月 14日
用户指南 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 2006年 11月 15日
用户指南 TMS320C64x DSP Two Level Internal Memory Reference Guide (Rev. C) 2006年 2月 28日
用户指南 TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 2006年 1月 1日
用户指南 TMS320C6000 DSP 外设概述参考指南 (Rev. H) 下载最新的英文版本 (Rev.Q) 2005年 11月 7日
应用手册 TMS320C6418 Hardware Designer's Resource Guide (Rev. A) 2005年 10月 25日
应用手册 TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A) 2005年 10月 20日
用户指南 TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 2005年 3月 1日
应用手册 TMS320C6418 Power Consumption Summary (Rev. A) 2005年 2月 2日
用户指南 TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 2005年 1月 25日
用户指南 TMS320C64x DSP Viterbi-Decoder Coprocessor (VCP) Reference Guide (Rev. D) 2004年 9月 20日
应用手册 Use and Handling of Semiconductor Packages With ENIG Pad Finishes 2004年 8月 31日
用户指南 TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 2004年 8月 13日
用户指南 TMS320C6410/13/18 DSP Inter-Integrated Circuit (I2C) Module Addendum to SPRU175 (Rev. A) 2004年 8月 13日
应用手册 TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 2004年 4月 26日
应用手册 TMS320C6000 Board Design: Considerations for Debug (Rev. C) 2004年 4月 21日
用户指南 TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 2004年 3月 25日
应用手册 TMS320C6000 McBSP Initialization (Rev. C) 2004年 3月 8日
应用手册 TMS320C6000 EDMA IO Scheduling and Performance 2004年 3月 5日
应用手册 TMS320C64x EDMA Performance Data 2004年 3月 5日
应用手册 TMS320C64x EDMA Architecture 2004年 3月 3日
应用手册 TMS320C64x DSP Host Port Interface (HPI) Performance 2003年 10月 24日
应用手册 Using TMS320C6416 Coprocessors: Viterbi Coprocessor (VCP) (Rev. D) 2003年 9月 15日
应用手册 TMS320C6000 EMIF to TMS320C6000 Host Port Interface (Rev. B) 2003年 9月 12日
用户指南 TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 2003年 7月 31日
应用手册 Using IBIS Models for Timing Analysis (Rev. A) 2003年 4月 15日
应用手册 TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 2002年 6月 4日
应用手册 TMS320C6000 Board Design for JTAG (Rev. C) 2002年 4月 2日
应用手册 TMS320C6000 EMIF to External Flash Memory (Rev. A) 2002年 2月 13日
应用手册 Cache Usage in High-Performance DSP Applications with the TMS320C64x 2001年 12月 13日
应用手册 Using a TMS320C6000 McBSP for Data Packing (Rev. A) 2001年 10月 31日
应用手册 TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 2001年 10月 24日
应用手册 TMS320C6000 Host Port to MC68360 Interface (Rev. A) 2001年 9月 30日
应用手册 TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 2001年 8月 31日
应用手册 TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 2001年 8月 31日
应用手册 Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 2001年 8月 31日
应用手册 TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 2001年 7月 23日
应用手册 TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 2001年 7月 10日
应用手册 TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 2001年 6月 30日
应用手册 TMS320C6000 Host Port to MPC860 Interface (Rev. A) 2001年 6月 21日
应用手册 TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 2001年 5月 21日
应用手册 Circular Buffering on TMS320C6000 (Rev. A) 2000年 9月 12日
应用手册 TMS320C6000 McBSP as a TDM Highway (Rev. A) 2000年 9月 11日
应用手册 TMS320C6000 Multichannel Communications System Interface 2000年 2月 3日
应用手册 TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 2000年 2月 2日
应用手册 General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 2000年 1月 31日
应用手册 TMS320C6000 C Compiler: C Implementation of Intrinsics 1999年 12月 7日
应用手册 TMS320C6000 McBSP: I2S Interface 1999年 9月 8日
应用手册 TMS320C6000 HPI Boot Operation 1999年 1月 6日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

调试探针

TMDSEMU560V2STM-U — Blackhawk XDS560v2 系统跟踪 USB 仿真器

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)

现货
数量限制: 1
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)

现货
数量限制: 1
驱动程序或库

SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

软件编解码器

ADT-3P-DSPVOIPCODECS — 自适应数字技术 DSP VOIP、语音和音频编解码器

Adaptive Digital 是音质增强算法的开发公司,提供可与 TI DSP 配合使用的一流声学回声消除软件。Adaptive Digital 在算法开发、实施、优化和配置调优方面具有丰富的经验。他们提供适用于语音技术、音质软件、回声消除、会议软件、语音压缩算法的解决方案和即用型解决方案。

如需了解有关 Adaptive Digital 的更多信息,请访问 https://www.adaptivedigital.com
由 Adaptive Digital Technologies, Inc. 提供
软件编解码器

COUTH-3P-DSPVOIPCODECS — CouthIT DSP VoIP、语音和音频编解码器

自 1999 年以来,CouthIT 一直帮助客户将其理念转换成强大可靠的实时软件解决方案。CouthIT 许可在 VoIP 以及语音和音频编解码器领域内使用预先构建且高度优化的专用软件模块,并为多媒体应用提供软件优化和定制服务。我们的目标客户是寻求 DSP 平台(包括 TI C5000™ DSP)上嵌入式软件模块支持的 OEM 和 ODM。

(...)
由 Couth Infotech Pvt. Ltd. 提供
软件编解码器

VOCAL-3P-DSPVOIPCODECS — Vocal Technologies DSP VoIP 编解码器

经过 25 年以上的组装和 C 代码开发,VOCAL 的模块化软件套件可用于各种各样的 TI DSP 产品。产品具体包括 ATA、VoIP 服务器和网关、基于 HPNA 的 IPBX、视频监控、语音和视频会议、语音和数据射频器件、RoIP 网关、政务安全器件、合法拦截软件、医疗设备、嵌入式调制解调器、T.38 传真和 FoIP。

如需了解有关 Vocal Technologies 的更多信息,请访问 https://www.vocal.com
由 VOCAL Technologies, Ltd. 提供
仿真模型

C6418 GTS IBIS Model

SPRM162.ZIP (96 KB) - IBIS Model
仿真模型

C6418 GTS BSDL Model (Rev. A)

SPRM163A.ZIP (7 KB) - BSDL Model
设计工具

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
封装 引脚 下载
FCBGA (GTS) 288 了解详情
FCBGA (ZTS) 288 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

视频