C64x fixed point DSP - 500MHz, McBSP, McASP, I2cC
产品详细信息
参数
封装|引脚|尺寸
特性
- High-Performance Fixed-Point Digital Signal Processor (TMS320C6413/C6410)
- TMS320C6413
- 2-ns Instruction Cycle Time
- 500-MHz Clock Rate
- 4000 MIPS
- TMS320C6410
- 2.5-ns Instruction Cycle Time
- 400-MHz Clock Rate
- 3200 MIPS
- Eight 32-Bit Instructions/Cycle
- Fully Software-Compatible With C64x™
- Extended Temperature Devices Available
- TMS320C6413
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
- Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
- Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache [C6413] (Flexible RAM/Cache Allocation)
- 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [C6410] (Flexible RAM/Cache Allocation)
- Endianess: Little Endian, Big Endian
- 32-Bit External Memory Interface (EMIF)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 512M-Byte Total Addressable External Memory Space
- Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
- Host-Port Interface (HPI) [32-/16-Bit]
- Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each
- Two Inter-Integrated Circuit (I2C) Buses
- Additional GPIO Capability
- Two Multichannel Buffered Serial Ports
- Three 32-Bit General-Purpose Timers
- Sixteen General-Purpose I/O (GPIO) Pins
- Flexible PLL Clock Generator
- On-Chip Fundamental Oscillator
- IEEE-1149.1 (JTAG
) Boundary-Scan-Compatible
- 288-Pin Ball Grid Array (BGA) Package (GTS and ZTS Suffixes), 1.0-mm Ball Pitch
- 0.13-µm/6-Level Cu Metal Process (CMOS)
- 3.3-V I/Os, 1.2-V Internal
VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
描述
The TMS320C64x DSPs (including the TMS320C6413, TMS320C6410 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C6413 and TMS320C6410 (C6413 and C6410) devices are based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI) The high-performance, lower-cost C6413/C6410 DSPs enable customers to reduce system costs for telecom, medical, industrial, office, and photo lab equipment. The C64x is a code-compatible member of the C6000 DSP platform.
With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C6413 device offers cost-effective solutions to high-performance DSP programming challenges.
With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the C6410 device offers cost-effective solutions to high-performance DSP programming challenges. The C6410 device also provides excellent value for packet telephony and for other cost-sensitive applications demanding high performance. The C6410 device also provides excellent value for packet telephony and to other cost-sensitive applications demanding high performance
The C6413/C6410 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional unitstwo multipliers for a 32-bit result and six arithmetic logic units (ALUs) with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI architecture. The C6413 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4000 MMACS. The C6410 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The C6413/C6410 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.
The C6413/C6410 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space [for C6413 device] and the Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space [for C6410 device]. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.
The McASP port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6413/C6410 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.
McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.
The I2C ports on the TMS320C6413/C6410 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
TheC6413/C6410 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
No design support from TI available
This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.
技术文档
设计与开发
有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。硬件开发
说明
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。
Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)
特性
XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。
XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。
XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。
与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。
所有 XDS560v2 (...)
说明
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。
Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)
特性
XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。
XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。
XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。
与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。
所有 XDS560v2 (...)
软件开发
特性
Image Analysis
- Image boundry and perimeter
- Morphological operation
- Edge detection
- Image Histogram
- Image thresholding
Image filtering and format conversion
- Color space conversion
- Image convolution
- Image correlation
- Error diffusion
- Median filtering
- Pixel expansion
Image compression and decompression
- Forward and (...)
特性
Optimized DSP routines including functions for:
- Adaptive filtering
- Correlation
- FFT
- Filtering and convolution: FIR, biquad, IIR, convolution
- Math: Dot products, max value, min value, etc.
- Matrix operations
设计工具和仿真
特性
- Supports many TI processors including Sitara and Jacinto Processors and DSPs
- Search by type of product, TI devices supported, or country
- Links and contacts for quick engagement
- Third-party companies located around the world
CAD/CAE 符号
封装 | 引脚 | 下载 |
---|---|---|
FCBGA (GTS) | 288 | 了解详情 |
FCBGA (ZTS) | 288 | 了解详情 |
订购与质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/FIT 估算
- 材料成分
- 认证摘要
- 持续可靠性监测