产品详细信息

DSP 1 C55x DSP MHz (Max) 100, 120, 150 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (C) -10 to 70, -40 to 85
DSP 1 C55x DSP MHz (Max) 100, 120, 150 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (C) -10 to 70, -40 to 85
NFBGA (ZCH) 196 100 mm² 10 x 10
  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-, 6.66-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-, 150-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200, 240, or 300 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • 16-bit SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL) and 10-bit SAR ADC (VDDA_ANA)
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.4-V Core (150 MHz), 1.8-V, 2.5-V, 2.75-V or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-, 6.66-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-, 150-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200, 240, or 300 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • 16-bit SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL) and 10-bit SAR ADC (VDDA_ANA)
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.4-V Core (150 MHz), 1.8-V, 2.5-V, 2.75-V or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (VDDA_PLL) and 10-bit SAR ADC(VDDA_ANA). Note: ANA_LDO can only provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external supply is required to supply 1.4 V to the DSP PLL (VDDA_PLL).

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (VDDA_PLL) and 10-bit SAR ADC(VDDA_ANA). Note: ANA_LDO can only provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external supply is required to supply 1.4 V to the DSP PLL (VDDA_PLL).

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

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Limited design support from TI available

This product has limited design support from TI for existing projects. If available, you will find relevant collateral, software and tools in the product folder. For existing designs using this product, you can request support in the TI E2ETM support forums, but limited support is available for this product.

技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 TMS320C5505 Fixed-Point Digital Signal Processor 数据表 (Rev. F) 2013年 8月 13日
* 勘误表 TMS320C5505/C5504 Fixed-Point DSP Silicon Errata (Silicon Revision 2.0) (Rev. D) 2015年 7月 15日
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 下载英文版本 (Rev.A) 2021年 5月 19日
应用手册 Using the TMS320C5515/14/05/04 Bootloader (Rev. D) 2019年 11月 25日
应用手册 TMS320C5505/15/35 Schematic Checklist 2019年 2月 14日
技术文章 Bringing the next evolution of machine learning to the edge 2018年 11月 27日
技术文章 How quality assurance on the Processor SDK can improve software scalability 2018年 8月 22日
技术文章 Clove: Low-Power video solutions based on Sitara™ AM57x processors 2016年 7月 21日
应用手册 Power Estimation and Pwr Consumption Sum for TMS320C5504/05/14/15/32/33/34/35 (Rev. A) 2016年 4月 4日
应用手册 Instructions to Benchmark C55 DSP Library 2016年 4月 1日
技术文章 TI's new DSP Benchmark Site 2016年 2月 8日
应用手册 C5000 DSP-Based Low-Power System Design 2015年 11月 30日
用户指南 TMS320C5515/14/05/04/VC05/VC04 DSP MMC/SD Card Controller User's Guide (Rev. B) 2015年 9月 30日
用户指南 TMS320C5515/14/05/04 DSP Universal Serial Bus 2.0 (USB) Controller User's Guide (Rev. A) 2013年 10月 3日
应用手册 FFT Implementation on the TMS320VC5505, TMS320C5505, and TMS320C5515 DSPs (Rev. B) 2013年 1月 9日
用户指南 TMS320C5515/14/05/04 DSP External Memory Interface (EMIF) User's Guide (Rev. B) 2012年 11月 18日
用户指南 TMS320C5515/14/05/04 DSP Real-Time Clock (RTC) User's Guide (Rev. A) 2012年 11月 15日
用户指南 TMS320C5505 DSP System User's Guide (Rev. B) 2012年 9月 14日
用户指南 TMS320C5515/14/05/04 DSP Inter-IC Sound (I2S) Bus User's Guide (Rev. B) 2012年 8月 9日
用户指南 TMS320C5515/14/05/04 DSP Direct Memory Access (DMA) Controller User's Guide (Rev. A) 2012年 3月 7日
用户指南 TMS320C5515/05/VC05 DSP Successive Approx. Register (SAR) ADC User's Guide (Rev. C) 2012年 1月 13日
应用手册 Migrating from TMS320C5515/05 to TMS320C5535/34/33/32 (Rev. A) 2011年 12月 22日
用户指南 TMS320C55x Assembly Language Tools User's Guide (Rev. I) 2011年 11月 9日
用户指南 TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. G) 2011年 11月 9日
更多文献资料 C5515 eZdsp (Rev. A) 2010年 11月 8日
更多文献资料 C5504/05 Product Bulletin 2010年 1月 12日
用户指南 Corazo'n Line22 2009年 9月 21日
用户指南 Corazo'n Line23 2009年 9月 21日
用户指南 Corazo'n Line24 2009年 9月 21日
用户指南 Corazo'n Line25 2009年 9月 21日
用户指南 Corazo'n Line33 2009年 9月 21日
用户指南 TMS320VC5505 DSP Inter-Integrated Circuit Peripheral User's Guide (Rev. A) 2009年 9月 21日
用户指南 TMS320C55x 3.0 DSP Algebraic Instruction Set Reference Guide (Rev. E) 2009年 6月 24日
用户指南 TMS320C55x 3.0 DSP Mnemonic Instruction Set Reference Guide (Rev. E) 2009年 6月 24日
用户指南 TMS320C55x DSP CPU Reference Guide, Version 3.0 (Rev. E) 2009年 6月 17日
用户指南 TMS320C55x Assembly Language Tools User's Guide (Rev. H) 2004年 7月 31日
用户指南 TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. F) 2003年 12月 31日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

评估板

TMDX5505EZDSP — C5505 eZdsp™ USB 记忆棒开发工具

TMDX5505eZDSP 是一款由 USB 供电的超低成本的小型 DSP 开发工具,它包含评估行业最低功耗的 16 位 DSP(TMS320C5504 和 TMS320C5505)所需的全部硬件和软件。USB 端口可为超低功耗 C5505 的运行提供足够的电源,无需外部电源。

此超低成本工具可快速轻松地评估 C5505 和 C5504 处理器的高级功能。此工具已嵌入用于完整的源代码级调试能力的 XDS510 仿真器,此外,该工具还支持 Code Composer Studio&trade (...)

现货
数量限制: 10
评估板

TMDX5515EZDSP — C5515 eZDSP USB 记忆棒开发工具

TMDX5515eZDSP 是一种由 USB 供电的超低成本的小型 DSP 开发工具,它包括评估业内最低功耗 16 位 DSP TMS320C5515 所需的所有硬件和软件。此工具在外形上类似于 TMDX5505eZdsp,但提供更多评估选项,如 USB2.0 和 SD 接口。USB (...)

现货
数量限制: 1
调试探针

TMDSEMU200-U — Spectrum Digital XDS200 USB 仿真器

Spectrum Digital XDS200 是最新 XDS200 系列 TI 处理器调试探针(仿真器)的首个模型。XDS200 系列拥有超低成本 XDS100 与高性能 XDS560v2 之间的低成本与高性能的完美平衡。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS200 通过 TI 20 引脚连接器(带有适合 TI 14 引脚、TI 10 引脚和 ARM 20 引脚的多个适配器)连接到目标板,而通过 USB2.0 高速连接 (480Mbps) 连接到主机 PC。要在主机 PC 上运行,还需要 Code Composer Studio™ IDE 许可证。

(...)

现货
数量限制: 3
调试探针

TMDSEMU560V2STM-U — Blackhawk XDS560v2 系统跟踪 USB 仿真器

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)

现货
数量限制: 1
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)

现货
数量限制: 1
应用软件和框架

C55X-AUDIOFRAMEWORK — C55x 已连接音频框架

TMS320C55x™ 已连接音频框架提供了一种允许 C55x 器件作为 USB 音频外设工作的软件框架。除了提供此功能外,框架可由用户在记录和回放路径中通过合并音频处理算法扩展。C55x 已连接音频框架还实施了 USB 人机界面设备 (HID) 类应用,可用于执行例如音量、播放和停止音频的功能。
驱动程序或库

SPRC100 — TMS320C55x DSP 库

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
驱动程序或库

SPRC133 — TMS320C55x 芯片支持库 (CSL) – 标准和低功耗

C55x 芯片支持库 (CSL) 提供一个应用程序编程接口 (API),用于配置和控制 DSP 片上外设以实现易用性、各种 C55x 器件间的兼容性以及硬件抽象。CSL 将通过标准化和可移植性来缩短开发时间。
  • C55x CSL (SPRC133):特性部分列出的功能是专为 TMS320C55x DSP(包括 C5501、C5502、C5509、C5509A 和 C5510、C5510A)设计的。
  • C55x CSL - 低功耗:特性部分列出的功能专为 TMS320C55x 低功耗 DSP(包括 C5504/05、C5514/15/17 和 C5535/45 器件)而设计。

特性

模块
名称
C55x CSL - SPRC133
外设说明
模块
名称
C55x CSL - 低功耗 CSL
外设说明
ADC 模数转换器 SAR 10 位 SAR ADC
ICACHE 指令缓存    
DAT 器件相关
数据复制/填充
DAT 数据复制/填充模块
基于 DMA C5505
DMA 直接存储器存取 DMA 直接存储器存取
IRQ 中断控制器 INTC 中断控制器
EMIF 外部存储器接口 NAND NAND 闪存
GPIO 通用 I/O GPIO 通用 I/O
GPT 32 位通用计时器 GPT 32 位通用计时器
主机端口接口 (HPI) 主机端口接口    
I2C I2C (...)
驱动程序或库

SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

软件编解码器

C55XCODECS — 编解码器 - 针对 C55x 器件进行了优化

TI 编解码器免费提供,附带生产许可且现在可供下载。全部经过生产测试,可轻松集成到音频和语音应用中。单击“获取软件”按钮(上方),以获取经过测试的最新编解码器版本。该页面及每个安装程序中都包含有数据表和发布说明。

 

 

其它信息:

软件编解码器

ADT-3P-DSPVOIPCODECS — 自适应数字技术 DSP VOIP、语音和音频编解码器

Adaptive Digital 是音质增强算法的开发公司,提供可与 TI DSP 配合使用的一流声学回声消除软件。Adaptive Digital 在算法开发、实施、优化和配置调优方面具有丰富的经验。他们提供适用于语音技术、音质软件、回声消除、会议软件、语音压缩算法的解决方案和即用型解决方案。

如需了解有关 Adaptive Digital 的更多信息,请访问 https://www.adaptivedigital.com
由 Adaptive Digital Technologies, Inc. 提供
软件编解码器

ALGOT-3P-DSPVOIPCODECS — Algotron C5000 DSP 电信和音频编解码器

Algotron 提供适用于电信和音频的 C5000 DSP 软件模块。示例包括:适用于 DTMF 和来电显示的现代数据泵、语音编码器、信号生成器和检测器。所有模块均采用简单灵活且支持完全重入的接口。所有模块均附带用户指南、示例应用和测试报告(如果适用)。可提供集成咨询。

如需了解有关 Algotron 的更多信息,请访问 http://www.algotron.com/audio/audio_sum.htm

由 Algotron 提供
软件编解码器

COUTH-3P-DSPVOIPCODECS — CouthIT DSP VoIP、语音和音频编解码器

自 1999 年以来,CouthIT 一直帮助客户将其理念转换成强大可靠的实时软件解决方案。CouthIT 许可在 VoIP 以及语音和音频编解码器领域内使用预先构建且高度优化的专用软件模块,并为多媒体应用提供软件优化和定制服务。我们的目标客户是寻求 DSP 平台(包括 TI C5000™ DSP)上嵌入式软件模块支持的 OEM 和 ODM。

(...)
由 Couth Infotech Pvt. Ltd. 提供
软件编解码器

DSPI-3P-DSPVOIPCODECS — DSP 创新:DSP VoIP 编解码器

DSP Innovations 是 C5000TM DSP 软件和工程服务的供应商。DSPINI 提供的专有和标准声码器具有优异的特性,工作速率为 300bps 至 64kbps,适用于以下领域:保密语音、软件定义的无线电、无线、VoIP、语音存储等。DSPINI 的团队凭借在数学密集算法和软件方面的深厚背景,可为每位客户提供最有利的解决方案。

如需了解有关 DSP Innovations 的更多信息,请访问:http://dspini.com

由 DSP Innovations 提供
软件编解码器

SCORP-3P-DSPAUDIOCODECS — Spirit DSP 音频和语音编解码器

自 1992 年成立以来,SPIRIT 已经成为一流语音、音频和数据通信软件产品领域的全球品牌,并因创新而闻名。SPIRIT 是一家技术型公司,将在智能电信运营商级解决方案领域的丰富经验应用于通过分组网络((IP、3G、Wi-Fi/WiMAX、LTE))进行语音和视频传输。遍布 80 多个国家的 1 亿多嵌入式语音通道均以 SPIRIT 的技术为基础。

如需了解有关 SPIRIT 的更多信息,请访问 https://www.spiritdsp.com
由 Spirit DSP 提供
软件编解码器

VOCAL-3P-DSPVOIPCODECS — Vocal Technologies DSP VoIP 编解码器

经过 25 年以上的组装和 C 代码开发,VOCAL 的模块化软件套件可用于各种各样的 TI DSP 产品。产品具体包括 ATA、VoIP 服务器和网关、基于 HPNA 的 IPBX、视频监控、语音和视频会议、语音和数据射频器件、RoIP 网关、政务安全器件、合法拦截软件、医疗设备、嵌入式调制解调器、T.38 传真和 FoIP。

如需了解有关 Vocal Technologies 的更多信息,请访问 https://www.vocal.com
由 VOCAL Technologies, Ltd. 提供
仿真模型

C5505 ZCH BSDL Model

SPRM500.ZIP (5 KB) - BSDL Model
仿真模型

C5505 ZCH IBIS Model

SPRM501.ZIP (445 KB) - IBIS Model
设计工具

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
封装 引脚 下载
NFBGA (ZCH) 196 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

推荐产品的参数、评估模块或参考设计可能与此 TI 产品相关

支持与培训

视频