TMS320C5505
- High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
- 16.67-, 13.33-, 10-, 8.33-, 6.66-ns Instruction Cycle Time
- 60-, 75-, 100-, 120-, 150-MHz Clock Rate
- One/Two Instructions Executed per Cycle
- Dual Multipliers [Up to 200, 240, or 300 Million Multiply-Accumulates per Second (MMACS)]
- Two Arithmetic/Logic Units (ALUs)
- Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
- Software-Compatible With C55x Devices
- Industrial Temperature Devices Available
- 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
- 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
- 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
- 128K Bytes of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit) - 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
- 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
- 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
- 8-/16-Bit NOR Flash
- Asynchronous Static RAM (SRAM)
- 16-bit SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
- Direct Memory Access (DMA) Controller
- Four DMA With 4 Channels Each (16-Channels Total)
- Three 32-Bit General-Purpose Timers
- One Selectable as a Watchdog and/or GP
- Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
- Universal Asynchronous Receiver/Transmitter (UART)
- Serial-Port Interface (SPI) With Four Chip-Selects
- Master/Slave Inter-Integrated Circuit (I2C Bus™)
- Four Inter-IC Sound (I2S Bus™) for Data Transport
- Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
- USB 2.0 Full- and High-Speed Device
- LCD Bridge With Asynchronous Interface
- Tightly-Coupled FFT Hardware Accelerator
- 10-Bit 4-Input Successive Approximation (SAR) ADC
- Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
- Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
- Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
- One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL) and 10-bit SAR ADC (VDDA_ANA)
- Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
- On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
- IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible - Up to 26 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions) - 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
- 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
- 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
- 1.4-V Core (150 MHz), 1.8-V, 2.5-V, 2.75-V or 3.3-V I/Os
All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.
The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.
The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.
The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.
The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.
In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.
The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (VDDA_PLL) and 10-bit SAR ADC(VDDA_ANA). Note: ANA_LDO can only provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external supply is required to supply 1.4 V to the DSP PLL (VDDA_PLL).
The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.
TI 仅提供有限的设计支持
该产品对现有工程提供的 TI 设计支持有限。如可用,您将在产品文件夹中找到相关的配套资料、软件和工具。对于使用该产品的现有设计,您可以在 TI E2ETM 支持论坛中申请支持,但针对该产品提供的支持有限。
技术文档
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
TMDSEMU200-U — XDS200 USB 调试探针
XDS200 是用于调试 TI 嵌入式器件的调试探针(仿真器)。与低成本的 XDS110 和高性能的 XDS560v2 相比,XDS200 在低成本和高性能之间实现了平衡;并在单个仓体中支持广泛的标准(IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪,则需要使用 XDS560v2 PRO TRACE。
XDS200 通过 TI 20 引脚连接器(带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)
TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针
XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意,它不支持串行线调试 (SWD)。
所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE。
XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)
TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)
C55XCSL-LOWPOWER — 适用于 C5504/05、C5514/15/17 和 C5535/45 器件的 TMS320C55x 芯片支持库
The C55x Chip Support Libraries (CSL) provide an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use, compatibility between various C55x devices and hardware abstraction. CSLs will shorten development time by providing (...)
支持的产品和硬件
产品
数字信号处理器 (DSP)
SPRC100 — TMS320C55x DSP 库
SPRC264 — TMS320C6000 图像库 (IMGLIB)
TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER
CCSTUDIO — Code Composer Studio 集成式开发环境 (IDE)
Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications. Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)
支持的产品和硬件
此设计资源支持这些类别中的大部分产品。
查看产品详情页,验证是否能提供支持。
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parametric-filter 数字信号处理器 (DSP) -
parametric-filter 基于 Arm 的处理器 -
parametric-filter MSP430 微控制器 -
parametric-filter C2000 实时微控制器 -
parametric-filter 基于 Arm 的微控制器 -
parametric-filter 信号调节器 -
parametric-filter 毫米波雷达传感器 -
parametric-filter Zigbee 产品 -
parametric-filter Wi-Fi 产品 -
parametric-filter Thread 产品 -
parametric-filter 其他无线技术 -
parametric-filter 低于 1GHz 产品 -
parametric-filter 多协议产品 -
parametric-filter 蓝牙产品 -
parametric-filter 数字电源隔离式控制器
ADT-3P-DSPVOIPCODECS — 自适应数字技术 DSP VOIP、语音和音频编解码器
如需了解有关 Adaptive Digital 的更多信息,请访问 https://www.adaptivedigital.com。
ALGOT-3P-DSPVOIPCODECS — Algotron C5000 DSP 电信和音频编解码器
如需了解有关 Algotron 的更多信息,请访问 http://www.algotron.com/audio/audio_sum.htm。
C55XCODECS — 编解码器 - 针对 C55x 器件进行了优化
其它信息:
- DSP 和 ARM 编解码器 - 当前库存 - 所有 TI 编解码器
- TI E2E™ 社区
DSPI-3P-DSPVOIPCODECS — DSP 创新:DSP VoIP 编解码器
如需了解有关 DSP Innovations 的更多信息,请访问:http://dspini.com。
VOCAL-3P-DSPVOIPCODECS — Vocal Technologies DSP VoIP 编解码器
如需了解有关 Vocal Technologies 的更多信息,请访问 https://www.vocal.com。
封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
NFBGA (ZCH) | 196 | Ultra Librarian |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
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