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TL28L92

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3.3V/5V 双通道通用异步接收器/发送器

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数据表

TL28L92

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产品详情

Number of channels 2 FIFO (Byte) 16 Rx FIFO trigger levels (#) 4 Tx FIFO trigger levels (#) 4 Programmable FIFO trigger levels Yes CPU interface X86 or 68K Baud rate at Vcc = 3.3 V & with 16x sampling (max) (MBps) 1 Baud rate at Vcc = 5 V & with 16x sampling (max) (MBps) 1 Operating voltage (V) 3.3, 5 Auto RTS/CTS Yes Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 2 FIFO (Byte) 16 Rx FIFO trigger levels (#) 4 Tx FIFO trigger levels (#) 4 Programmable FIFO trigger levels Yes CPU interface X86 or 68K Baud rate at Vcc = 3.3 V & with 16x sampling (max) (MBps) 1 Baud rate at Vcc = 5 V & with 16x sampling (max) (MBps) 1 Operating voltage (V) 3.3, 5 Auto RTS/CTS Yes Rating Catalog Operating temperature range (°C) -40 to 85
QFP (FR) 44 153.76 mm² 12.4 x 12.4
  • 3.3V to 5V, –40°C to 85°C and 68xxx or 80xxx bus interface
  • Dual full-duplex independent asynchronous receiver and transmitters 16 Character FIFOs for each receiver and transmitter
  • Pin programming selects 68xxx or 80xxx bus interface
  • Programmable data format
    • 5 Data to 8 data bits plus parity
    • Odd, even, no parity or force parity
    • 1 stop, 1.5 stop or 2 stop bits programmable in 1/16-bit increments
  • 16-Bit programmable counter and timer
  • Programmable baud rate for each receiver and transmitter selectable from:
    • 28 Fixed rates: 50Bd to 230.4kBd
    • Other baud rates to 1MHz at 16×
    • Programmable user-defined rates derived from a programmable counter and timer
    • External 1× or 16× Clock
  • Parity, framing, and overrun error detection
  • False start bit detection
  • Line break detection and generation
  • Programmable channel mode
    • Normal (full-duplex)
    • Automatic echo
    • Local loopback
    • Remote loopback
  • Multi-function 7-bit input port (includes IACKN)
    • Can serve as clock or control inputs
    • Change of state detection on four inputs have typically > 100kΩ pullup resistors
    • Change of state detectors for modem control
  • Multi-function 8-Bit output port
    • Individual bit set and reset capability
    • Outputs can be programmed to be status and interrupt signals
    • FIFO status for DMA interface
  • Versatile interrupt system
    • Single interrupt output with eight maskable interrupting conditions
    • Output port can be configured to provide a total of up to five separate interrupt outputs that may be wire ORed
    • Each FIFO can be programmed for four different interrupt levels
    • Watchdog timer for each receiver
  • Maximum data transfer rates: 1× – 1Mbits, 16× – 1Mbit/s
  • Start-end break interrupt and status
  • Detects break which originates in the middle of a character
  • On-chip crystal oscillator
  • Power down mode
  • Receiver time-out mode
  • Single 3.3V or 5V power supply
  • Meets or exceeds JEDEC 14C ESD requirements
  • 3.3V to 5V, –40°C to 85°C and 68xxx or 80xxx bus interface
  • Dual full-duplex independent asynchronous receiver and transmitters 16 Character FIFOs for each receiver and transmitter
  • Pin programming selects 68xxx or 80xxx bus interface
  • Programmable data format
    • 5 Data to 8 data bits plus parity
    • Odd, even, no parity or force parity
    • 1 stop, 1.5 stop or 2 stop bits programmable in 1/16-bit increments
  • 16-Bit programmable counter and timer
  • Programmable baud rate for each receiver and transmitter selectable from:
    • 28 Fixed rates: 50Bd to 230.4kBd
    • Other baud rates to 1MHz at 16×
    • Programmable user-defined rates derived from a programmable counter and timer
    • External 1× or 16× Clock
  • Parity, framing, and overrun error detection
  • False start bit detection
  • Line break detection and generation
  • Programmable channel mode
    • Normal (full-duplex)
    • Automatic echo
    • Local loopback
    • Remote loopback
  • Multi-function 7-bit input port (includes IACKN)
    • Can serve as clock or control inputs
    • Change of state detection on four inputs have typically > 100kΩ pullup resistors
    • Change of state detectors for modem control
  • Multi-function 8-Bit output port
    • Individual bit set and reset capability
    • Outputs can be programmed to be status and interrupt signals
    • FIFO status for DMA interface
  • Versatile interrupt system
    • Single interrupt output with eight maskable interrupting conditions
    • Output port can be configured to provide a total of up to five separate interrupt outputs that may be wire ORed
    • Each FIFO can be programmed for four different interrupt levels
    • Watchdog timer for each receiver
  • Maximum data transfer rates: 1× – 1Mbits, 16× – 1Mbit/s
  • Start-end break interrupt and status
  • Detects break which originates in the middle of a character
  • On-chip crystal oscillator
  • Power down mode
  • Receiver time-out mode
  • Single 3.3V or 5V power supply
  • Meets or exceeds JEDEC 14C ESD requirements

The TL28L92 operates at 3.3V or 5V supply with added features and deeper FIFOs. The configuration on power-up is 16 character receiver, 16 character transmit FIFOs, watchdog timer for each receiver, mode register 0 is added, extended baud rate and overall faster speeds, programmable receiver and transmitter interrupts.

Pin programming allows the device to operate with either the Motorola or Intel bus interface. The bit 3 of the MR0A register allows the device to operate in an 8 byte FIFO mode.

The Texas Instruments TL28L92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. the device interfaces directly with microprocessors, and can be used in a polled or interrupt driven system with modem and DMA interface.

The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select an operating speed as one of 28 fixed baud rates; a 16× clock derived from a programmable counter/timer, or an external 1× or 16× clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems.

Each receiver and transmitter is buffered by 8 or 16 character FIFOs to minimize the potential of receiver overrun, transmitter underrun, and to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided via RTS/CTS signaling to disable a remote transmitter when the receiver buffer is full. Also provided on the TL28L92 is a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control.

The TL28L92 is available now in 44-pin QFP (FR).

The TL28L92 operates at 3.3V or 5V supply with added features and deeper FIFOs. The configuration on power-up is 16 character receiver, 16 character transmit FIFOs, watchdog timer for each receiver, mode register 0 is added, extended baud rate and overall faster speeds, programmable receiver and transmitter interrupts.

Pin programming allows the device to operate with either the Motorola or Intel bus interface. The bit 3 of the MR0A register allows the device to operate in an 8 byte FIFO mode.

The Texas Instruments TL28L92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. the device interfaces directly with microprocessors, and can be used in a polled or interrupt driven system with modem and DMA interface.

The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select an operating speed as one of 28 fixed baud rates; a 16× clock derived from a programmable counter/timer, or an external 1× or 16× clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems.

Each receiver and transmitter is buffered by 8 or 16 character FIFOs to minimize the potential of receiver overrun, transmitter underrun, and to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided via RTS/CTS signaling to disable a remote transmitter when the receiver buffer is full. Also provided on the TL28L92 is a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control.

The TL28L92 is available now in 44-pin QFP (FR).
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* 数据表 TL28L92 3.3V to 5V Dual Universal Asynchronous Receiver and Transmitter 数据表 (Rev. C) PDF | HTML 2024年 4月 26日

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  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
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