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参数

Function Clock synthesizer, Clock multiplier, Clock divider Number of outputs 6 Output frequency (Max) (MHz) 167 VCC core (V) 3.3 VCC out (V) 3.3 Input type XTAL, Differential, LVCMOS Output type LVCMOS Operating temperature range (C) 0 to 70 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC), I2C Rating Catalog open-in-new 查找其它 时钟发生器

封装|引脚|尺寸

TSSOP (PW) 20 42 mm² 6.5 x 6.4 open-in-new 查找其它 时钟发生器

特性

  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • EEPROM Programming Without the Need to Apply High Programming Voltage
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typ 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock™)
  • Packaged in 20-Pin TSSOP

Pro-Clock is a trademark of Texas Instruments.

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描述

The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE906 is characterized for operation from 0°C to 70°C.

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技术文档

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类型 标题 下载最新的英文版本 发布
* 数据表 Programmable 3-PLL Clock Synthesizer / Multiplier / Divider 数据表 2007年 12月 11日
应用手册 High Speed Layout Guidelines 2017年 8月 8日
技术文章 How to select an optimal clocking solution for your FPGA-based design 2015年 12月 9日
技术文章 Clocking sampled systems to minimize jitter 2014年 7月 31日
技术文章 Timing is Everything: How to optimize clock distribution in PCIe applications 2014年 3月 28日
用户指南 CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual 2010年 11月 22日
应用手册 Troubleshooting I2C 2009年 10月 19日
用户指南 CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual 2008年 12月 9日
应用手册 CDCx706/x906 Termination and Signal Integrity Guidelines 2007年 11月 28日
用户指南 CDCE906/CDCE706 Programming EVM 2007年 8月 14日
用户指南 CDCE906/CDCE706 Performance EVM 2007年 4月 17日
应用手册 Clock Recommendations for the DM643x EVM 2006年 11月 29日
应用手册 Recommended Input Terminations for the Differential Inputs of CDCE906/CDCE706 2006年 8月 10日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

硬件开发

评估板 下载
CDCE906 and CDCE706 EVM
CDCE906-706PERFEVM
document-generic 用户指南
$149.00
评估板 下载
document-generic 用户指南
$149.00
用于评估模块 (EVM) 的 GUI 下载
SCAC073F.ZIP (88940 KB)

软件开发

应用软件和框架 下载
SCAC097A.ZIP (14050 KB)
编程工具 下载
ClockPro™ 程序设计软件
CLOCKPRO TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:
  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

特性
  • Easy and fast device programming through EEPROM, I2C
  • Based on Labview

设计工具和仿真

仿真模型 下载
SCAC071A.ZIP (119 KB) - IBIS Model
GERBER 文件 下载
SCAC074.ZIP (963 KB)
GERBER 文件 下载
SCAC075.ZIP (847 KB)

参考设计

参考设计 下载
具有 Δ-Σ 调制器的基于分流器的隔离型电流感应模块参考设计
TIDA-00080 这种基于分流器的隔离式电流测量单元无需使用电流互感器 (CT) 即可实现高精度电流测量。通过整合了高压隔离功能和 Delta-Sigma 调制器的 AMC1304 来实现隔离。此解决方案避免了使用 CT 的必要,这是客户十分重视的一点,因为这可以减小电路板尺寸、降低产品重量、减轻系统中的串扰和 EMI,此外通过将 CT 替换为分流器可减少机械问题,从而潜在延长产品使用寿命。
document-generic 原理图 document-generic 用户指南
参考设计 下载
隔离式电流分流和电压测量参考设计
TIDA-00171 此评估套件和参考设计在 C2000™ TMS320F28377D Delfino™ 微控制器中实现了 AMC130x 加强版隔离式 Delta-Sigma 调制器以及集成式正弦滤波器。此设计让您能够评估这些测量值的性能:三个电机电流、三个逆变器电压以及直流链路电压。套件中提供了固件来配置正弦滤波器、设置 PLL 频率以及接收来自正弦滤波器的数据。此外,还提供一个多功能运行时 GUI 来帮助用户验证 AMC130x 性能,并支持 Delfino 控制器中的正弦滤波器参数的配置更改。
document-generic 原理图 document-generic 用户指南 document-generic 下载英文版本 (Rev.A)

CAD/CAE 符号

封装 引脚 下载
TSSOP (PW) 20 视图选项

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