SPRACP6 December 2019 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
This application report provides several suggestions on maximizing the GPIO resources on the device to limit the need for IO expanders. Most of the content in this report is catered towards the TMS320F28004x series but can be adapted for other C2000 real-time controllers.
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With the integration trend of microcontrollers, new C2000 devices now provide more analog peripherals, which reduce the system level cost and design effort. The F28004x device incorporates on-chip analog-to-digital converters (ADCs), buffered digital-to-analog converters (DACs), programmable gain amplifiers (PGAs), and comparator subsystems (CMPSS). However, the addition of all this extra analog along with their required pins has led to the reduction in the number of GPIOs. This document explores several options on how to maximize usage of GPIOs.
On every reset, the device executes a boot sequence in ROM depending on the boot mode configuration. By default, the boot ROM uses two boot control GPIO pins to determine the boot mode configuration. Table 1 shows the default boot mode options of the F28004x device.
Boot Mode | GPIO24 (default boot mode select pin 1) | GPIO32 (default boot mode select pin 0) |
---|---|---|
Parallel IO | 0 | 0 |
SCI/Wait boot | 0 | 1 |
CAN | 1 | 0 |
Flash | 1 | 1 |
There are two ways the boot control GPIO pins can be re-purposed for use in an application:
By using weak pull-ups on the boot control GPIO pins, the device will always boot to Flash boot mode. However, after boot completion, the boot control GPIO pins can be configured for application use. When utilizing this approach, the internal pull-ups should not be enabled on these GPIOs. It is recommended to use pull-up resistors in the range of 16.5 kΩ to 27.5 kΩ.
NOTE
The boot control GPIO pins should not be driven by anything else while the device is booting as that can influence the mode the device boots into.
Instead of dedicating a set of GPIOs to determine boot mode, the boot mode of the device can be configured as a zero pin option.
With the introduction of the F28004x and newer devices, the number of boot mode select pins can now be customized to support as many as three and as few as zero pins. Using the zero pin option restricts the device to a single boot mode but it frees up the factory default pins to be used for GPIO purposes. Contrary to previous devices which only allowed reconfiguration of the fourth boot mode entry, for the F28004x device, the whole boot mode selection table is customizable. The steps below outline how the device can be configured for zero pin boot to flash:
This is achieved by configuring BOOT_DEF_LOW (0xFFFFFF03) and BOOT_DEF_HIGH (0xFFFFFFFF) user OTP locations as shown in Table 2.
Boot Mode Number | BOOTDEF Name | Value |
---|---|---|
0 | BOOT_DEF0 | 03(Flash boot) |
1 | BOOT_DEF1 | 0xFF |
2 | BOOT_DEF2 | 0xFF |
3 | BOOT_DEF3 | 0xFF |
4 | BOOT_DEF4 | 0xFF |
5 | BOOT_DEF5 | 0xFF |
6 | BOOT_DEF6 | 0xFF |
7 | BOOT_DEF7 | 0xFF |
All the above custom boot configurations take effect by programming the related locations in user-configurable DCSM OTP. The steps below outline one way that can be achieved:
#pragma RETAIN(otp_z1_data_1)
#pragma DATA_SECTION(otp_z1_data_1,"dcsm_zsel_z1_1");
const long otp_z1_data_1 = 0x5AFFFFFF;
#pragma RETAIN(otp_z1_data_2)
#pragma DATA_SECTION(otp_z1_data_2,"dcsm_zsel_z1_2");
const long otp_z1_data_2 = 0xFFFFFF03;
MEMORY
{
PAGE 0:
DCSM_ZSEL_Z1_P0: origin = 0x07800C, length = 0x000002
DCSM_ZSEL_Z1_P1: origin = 0x07801C, length = 0x000002
}
SECTIONS
{
dcsm_zsel_z1_1 : > DCSM_ZSEL_Z1_P0, PAGE = 0
dcsm_zsel_z1_2 : > DCSM_ZSEL_Z1_P1, PAGE = 0
}
For detailed information on the above configurations, see the Device Boot Modes chapter in the TMS320F28004x Piccolo Microcontrollers Technical Reference Manual.
NOTE
OTP locations cannot be re-written, so it is strongly suggested that the Emulation Boot Mode be used to validate the custom modification first. EMU-BOOTPIN-CONFIG and EMU-BOOTDEF can be programmed to experiment with different boot modes without writing to OTP.