ZHCU763 March   2021

 

  1.   说明
  2.   资源
  3.   特性
  4.   应用
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Multichannel SSR with Independent Isolation Between SSR Channels
      2. 2.2.2 Design Challenge With Single Isolation
      3. 2.2.3 Multichannel SSR Drive With Single Isolation Multichannel Digital Isolator
      4. 2.2.4 Need of High-Impedance Voltage Translator
      5. 2.2.5 Design to Minimize Cross-Coupling and MOSFET Gate Pick up Due to Other SSR Switching
      6. 2.2.6 Schematic: Design of Gate-Drive Circuit
        1. 2.2.6.1 Calculation of Gate-Driver Power Consumption
      7. 2.2.7 Schematic: Digital Isolator Circuit
      8. 2.2.8 Schematic: 3.3 V to 10V_ISO, 5V_ISO Power Supply
    3. 2.3 Highlighted Products
      1. 2.3.1 ISO7760
      2. 2.3.2 ISO7740
      3. 2.3.3 ISO7041
      4. 2.3.4 CSD19538Q2
      5. 2.3.5 CSD17382F4
      6. 2.3.6 TPL7407LA
      7. 2.3.7 TLV760
      8. 2.3.8 TLC555
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Test Equipment Needed to Validate Board
      2. 3.1.2 Test Conditions
      3. 3.1.3 Test Procedure
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Functional Tests
      2. 3.3.2 Overcurrent Testing With External Fuse
      3. 3.3.3 Surge Testing
      4. 3.3.4 Multichannel SSR Driven From Two 24-VAC Transformers
      5. 3.3.5 Alternate SSR Topology for High Voltage
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 支持资源
    4. 4.4 Trademarks
  10. 5About the Author

2.3.6 TPL7407LA

The TPL7407LA device is a 30-V, high-current NMOS transistor array. This device consists of seven NMOS transistors with common-cathode clamp diodes for switching inductive loads. The maximum drain-current rating of a single NMOS channel is 600 mA. New regulation and drive circuitry is added to give maximum drive strength across all GPIO ranges (1.8 V–5 V). The key benefit of the TPL7407LA is its improved power efficiency and lower leakage than a bipolar Darlington implementation.

The design needs a low-side switch at the output of the digital isolator to interface to the PNP transistor of the gate-drive circuit. The gate-drive power supply is around 10 V; therefore, the TPL7407LA provides adequate design margins and a compact size with good integration.