ZHCSW49C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2说明
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 接收文档更新通知
    2. 7.2 支持资源
    3. 7.3 商标
    4. 7.4 静电放电警告
    5. 7.5 术语表
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

4.3 Static Characteristics for 3.3V Operation

VCC = 3.3V ±10 %; Tamb = –40°C to 85°C (unless otherwise noted)(1)(2)
SYMBOLPARAMETERTEST CONDITIONSMINTYPMAXUNIT
VILLow-level input voltage0.650.2 × VCCV
VIHHigh-level input voltage2.41.7V
VOLLow-level output voltageIOL = 2.4mA0.20.4V
VOHHigh-level output voltageexcept open-drain outputs(3);
IOH = –400μA		VCC – 0.5VCC – 0.2V
II(1XPD)Power-down mode input current on pin X1/CLKVI = 0V to VCC0.50.050.5μA
IIL(X1)Low-level operating input current on pin X1/CLKVI = 0V0μA
IIH(X1)HIgh-level operating input current on pin X1/CLKVI = VCC130μA
IIInput leakage currentVI = 0V to VCC,all except input port pins–0.50.050.5μA
input port pins(4)–8–20.5
IOZHHigh-level output OFF current
(3-state data bus)		VI = VCC0.5μA
IOZLLow-level output OFF current
(3-state data bus)		VI = 0V–0.5μA
IODLLow-level output current in OFF state (open drain)VI = 0V–0.5μA
IODHHigh-level output current in OFF state (open drain)VI = VCC0.5μA
ICCPower supply currentCMOS input levels,(5)Operating mode46mA
Power-down mode1525μA
(1) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4V and 3V with a transition time of 5ns maximum. For X1/CLK this swing is between 0.4V and 0.8 × VCC. All time measurements are referenced at input voltages of 0.8V and 2V, and output voltages of 0.8V and 2V, as appropriate.
(2) Typical values are at 25°C, typical supply voltages, and typical processing parameters.
(3) Test conditions for outputs: CL = 125pF, except open-drain outputs. Test conditions for open-drain outputs: CL = 125pF, constant current source = 2.6mA.
(4) Input port pins have active pull-up transistors that will source a typical 2 μA from VCC when the input pins are at VSS. Input port pins at VCC source 0μA.
(5) All outputs are disconnected. Inputs are switching between CMOS levels of VCC – 0.2V and VSS + 0.2V.