ZHCSW49C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2说明
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 接收文档更新通知
    2. 7.2 支持资源
    3. 7.3 商标
    4. 7.4 静电放电警告
    5. 7.5 术语表
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

6.2 Condensed Register Bit Formats

Table 6-4 Mode Register 0 (MR0)
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RxWATCHDOGRxINT[2]TxINT[1:0]FIFOSIZEBUADRATE EXTENDED IITEST2BAUDRATE EXTENDED1
Table 6-5 Mode Register 1 (MR1)
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RxRTS controlRxINT[1]ERRORMODEPARITYMODEPARITYTYPEbits per character
Table 6-6 Mode Register 2 (MR2)
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channel modeRTSN Control TxCTSN Enable Txstop bit length
Table 6-7 Clock Select Register (CSR)
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receiver clock select codetransmitter clock select code
Table 6-8 Command Register (CR)
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channel command codedisable Txenable Txdisable Rxenable Rx
Table 6-9 Channel Status Register (SR)
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received breakframing errorparity erroroverrun errorTxEMTTxRDYRxFULLRxRDY
Table 6-10 Interrupt Mask Register (Enables Interrupts) (IMR)
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change input portchange break BRxRDYBTxRDTYBcounter readychange break ARxRDYATxRDYA
Table 6-11 Interrupt Status Register (ISR)
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input port changechange break BRxRDYB FFULLBTxRDTYBcounter readychange break ARxRDYA FFULLATxRDYA
Table 6-12 Counter/Timer Preset Register, Upper (CTPU)
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8 MSB of the BRG timer divisor
Table 6-13 Counter/Timer Preset Register, Lower (Enables Interrupts) (CTPL)
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8 LSB of the BRG timer divisor
Table 6-14 Auxiliary Control Register and Change of State Control (ACR)
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BRG set selectcounter/timer mode and clock source select
(see Table 6-51)		enable IP3
COS interrupt		enable IP2
COS interrupt		enable IP1
COS interrupt		enable IP0
COS interrupt
Table 6-15 Input Port Change Register (IPCR)
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delta IP3delta IP2delta IP1delta IP0state of IP3state of IP2state of IP1state of IP0
Table 6-16 Input Port Register (IPR)
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state of IP7state of IP6state of IP5state of IP4state of IP3state of IP2state of IP1state of IP0
Table 6-17 Set Output Port Bits Register (SOPR)
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set OP7set OP6set OP5set OP4set OP3set OP2set OP1set OP0
Table 6-18 Reset Output Port Bits Register (ROPR)
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reset OP7reset OP6reset OP5reset OP4reset OP3reset OP2reset OP1reset OP0
Table 6-19 Output Port Configuration Register (OPCR)(1)
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configure OP7configure OP6configure OP5configure OP4configure OP3configure OP2configure OP1configure OP0
(1) OP1 and OP0 are the RTSN output and are controlled by the MR register