ZHCSIV8B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
DRC hold time is intended to slow the start of decay for a specified period of time in response to a decrease in energy level. To minimize audible artifacts, TI recommends to set the DRC hold time to 0 through programming page 0 / register 69, bits D6–D3 = 0000.