ZHCSIV8B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
All features on this device are addressed using the I2C bus. All of the writable registers can be read back. However, some registers contain status information or data, and are only available for reading.
The device contains several pages of 8-bit registers, and each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device. The pages defined for the device are 0, 1, 3, 8–9, 12–13 (DAC coefficient pages). Page 0 is the default home page after RESET. Page control occurs by writing a new page value into register 0 of the current page.
The control registers for the device are described in detail as follows. All registers are 8 bits in width, with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit.
Pages 0, 1, 3, 8–9, and 12–13 are available for use. All other pages and registers are reserved. Do not read from or write to reserved pages and registers. Also, do not write other than the reset values for the reserved bits and read-only bits of non-reserved registers; otherwise, device functionality failure can occur.
NOTE
Note that the page and register numbers are shown in decimal format. For use in microcode, these decimal values may need to be converted to hexadecimal format. For convenience, the register numbers are shown in both formats, whereas the page numbers are shown only in decimal format.
PAGE NUMBER | DESCRIPTION |
---|---|
0 | Page 0 is the default page on power up. Configuration for serial interface, digital I/O, and other circuitry. |
1 | Configuration for DAC, output drivers, volume controls, and other circuitry. |
3 | Register 16 controls the MCLK divider that controls the interrupt pulse duration, debounce timing, and detection-block clock. |
8–9 | DAC filter and DRC coefficients (buffer A) |
12–13 | DAC filter and DRC coefficients (buffer B) |