ZHCSHV3A March   2018  – November 2018 LMX8410L

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Configurations and Feature Description
        1. 7.3.1.1 RF, LO and IF Interfaces
          1. 7.3.1.1.1 RF Interface
          2. 7.3.1.1.2 LO Interface
            1. 7.3.1.1.2.1 LO Interface as Output Port
            2. 7.3.1.1.2.2 LO Interface as Input Port
          3. 7.3.1.1.3 Baseband Interface
        2. 7.3.1.2 Device Configurations Overview
          1. 7.3.1.2.1 Initialize the Device
          2. 7.3.1.2.2 Configure LO Modes
          3. 7.3.1.2.3 Set Up External LO Clock
          4. 7.3.1.2.4 Perform DCOC (DC Offset Correction)
          5. 7.3.1.2.5 Turn Off SM Clock
          6. 7.3.1.2.6 Perform IMRR (Image Rejection Ratio) Calibration
        3. 7.3.1.3 State Machine Clock
          1. 7.3.1.3.1 Set Divider Values For Internal LO Mode
          2. 7.3.1.3.2 Set Divider Values For External LO Mode
        4. 7.3.1.4 DCOC (DC Offset Correction)
          1. 7.3.1.4.1 RF Input Power Restriction During DCOC
          2. 7.3.1.4.2 Set Up DCOC Clock Divider
        5. 7.3.1.5 Image Rejection Calibration
          1. 7.3.1.5.1 Phase Calibration
          2. 7.3.1.5.2 Gain Calibration
        6. 7.3.1.6 IF Amplifier Common Mode Configurations
        7. 7.3.1.7 Synchronization Mode (Internal LO Mode Only)
          1. 7.3.1.7.1 Synchronization of the LO_OUT Output to the Fosc Input
          2. 7.3.1.7.2 Synchronization of I/Q Outputs to Fosc Inputs Using Internal LO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Internal LO Mode
        1. 7.4.1.1 VCO Range Uncertainty for 7.5 to 7.7 GHz
      2. 7.4.2 External LO Mode
    5. 7.5 Programming
      1. 7.5.1 General Comments Regarding Programming
      2. 7.5.2 Recommended Initial Power Up Sequence
      3. 7.5.3 Recommended and Power on Reset Bit Values
    6. 7.6 Register Map
      1. 7.6.1  R0 Register (Address = 0x0) [reset = X]
        1. Table 9. R0 Register Field Descriptions
      2. 7.6.2  R1 Register (Address = 0x1) [reset = 0x3]
        1. Table 10. R1 Register Field Descriptions
      3. 7.6.3  R2 Register (Address = 0x2) [reset = X]
        1. Table 11. R2 Register Field Descriptions
      4. 7.6.4  R9 Register (Address = 0x9) [reset = X]
        1. Table 12. R9 Register Field Descriptions
      5. 7.6.5  R10 Register (Address = 0xA) [reset = 0x80]
        1. Table 13. R10 Register Field Descriptions
      6. 7.6.6  R11 Register (Address = 0xB) [reset = 0x10]
        1. Table 14. R11 Register Field Descriptions
      7. 7.6.7  R14 Register (Address = 0xE) [reset = 0x70]
        1. Table 15. R14 Register Field Descriptions
      8. 7.6.8  R36 Register (Address = 0x24) [reset = 0x64]
        1. Table 16. R36 Register Field Descriptions
      9. 7.6.9  R37 Register (Address = 0x25) [reset = 0x200]
        1. Table 17. R37 Register Field Descriptions
      10. 7.6.10 R38 Register (Address = 0x26) [reset = 0x0]
        1. Table 18. R38 Register Field Descriptions
      11. 7.6.11 R39 Register (Address = 0x27) [reset = 0x2710]
        1. Table 19. R39 Register Field Descriptions
      12. 7.6.12 R40 Register (Address = 0x28) [reset = 0x0]
        1. Table 20. R40 Register Field Descriptions
      13. 7.6.13 R41 Register (Address = 0x29) [reset = 0x0]
        1. Table 21. R41 Register Field Descriptions
      14. 7.6.14 R42 Register (Address = 0x2A) [reset = 0x0]
        1. Table 22. R42 Register Field Descriptions
      15. 7.6.15 R43 Register (Address = 0x2B) [reset = 0x0]
        1. Table 23. R43 Register Field Descriptions
      16. 7.6.16 R44 Register (Address = 0x2C) [reset = 0xA2]
        1. Table 24. R44 Register Field Descriptions
      17. 7.6.17 R46 Register (Address = 0x2E) [reset = 0x1]
        1. Table 25. R46 Register Field Descriptions
      18. 7.6.18 R58 Register (Address = 0x3A) [reset = 0x8000]
        1. Table 26. R58 Register Field Descriptions
      19. 7.6.19 R59 Register (Address = 0x3B) [reset = 0x1]
        1. Table 27. R59 Register Field Descriptions
      20. 7.6.20 R69 Register (Address = 0x45) [reset = 0x0]
        1. Table 28. R69 Register Field Descriptions
      21. 7.6.21 R70 Register (Address = 0x46) [reset = 0xC350]
        1. Table 29. R70 Register Field Descriptions
      22. 7.6.22 R75 Register (Address = 0x4B) [reset = 0x0]
        1. Table 30. R75 Register Field Descriptions
      23. 7.6.23 R78 Register (Address = 0x4E) [reset = 0x0]
        1. Table 31. R78 Register Field Descriptions
      24. 7.6.24 R79 Register (Address = 0x4F) [reset = 0x7000]
        1. Table 32. R79 Register Field Descriptions
      25. 7.6.25 R80 Register (Address = 0x50) [reset = 0xA]
        1. Table 33. R80 Register Field Descriptions
      26. 7.6.26 R81 Register (Address = 0x51) [reset = 0x0]
        1. Table 34. R81 Register Field Descriptions
      27. 7.6.27 R82 Register (Address = 0x52) [reset = 0x23]
        1. Table 35. R82 Register Field Descriptions
      28. 7.6.28 R83 Register (Address = 0x53) [reset = 0x2000]
        1. Table 36. R83 Register Field Descriptions
      29. 7.6.29 R84 Register (Address = 0x54) [reset = 0x1900]
        1. Table 37. R84 Register Field Descriptions
      30. 7.6.30 R88 Register (Address = 0x58) [reset = 0x0]
        1. Table 38. R88 Register Field Descriptions
      31. 7.6.31 R94 Register (Address = 0x5E) [reset = 0x8080]
        1. Table 39. R94 Register Field Descriptions
      32. 7.6.32 R95 Register (Address = 0x5F) [reset = X]
        1. Table 40. R95 Register Field Descriptions
      33. 7.6.33 R103 Register (Address = 0x67) [reset = X]
        1. Table 41. R103 Register Field Descriptions
      34. 7.6.34 R110 Register (Address = 0x6E) [reset = X]
        1. Table 42. R110 Register Field Descriptions
      35. 7.6.35 R111 Register (Address = 0x6F) [reset = 0x0]
        1. Table 43. R111 Register Field Descriptions
      36. 7.6.36 R112 Register (Address = 0x70) [reset = 0x0]
        1. Table 44. R112 Register Field Descriptions
      37. 7.6.37 R121 Register (Address = 0x79) [reset = 0x0]
        1. Table 45. R121 Register Field Descriptions
      38. 7.6.38 R123 Register (Address = 0x7B) [reset = 0x3]
        1. Table 46. R123 Register Field Descriptions
      39. 7.6.39 R126 Register (Address = 0x7E) [reset = X]
        1. Table 47. R126 Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 High Frequency Trace Routing
      2. 10.1.2 Power Trace Routing
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

7.6 Register Map

This device has 128 registers from R0 to R127. They must be programmed in REVERSE order. Note that there are several registers that have no description, but they still need to be programmed as the power on reset value is not always the correct value. The complete listing for all registers, including those not described in this datasheet are available on the Registers tab on the TI TICSPro software.

Table 6. Full Register Map

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 0 SYNC_PHASE_PLL 1 0 0 0 OUT_MUTE FCAL_HPFD_ADJ 0 0 1 FCAL_EN MUXOUT_SEL RESET_PLL PLL_PD
R1 0 0 0 0 1 0 0 0 0 0 0 0 1 CAL_CLK_DIV
R2 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0
R3 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0
R4 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1
R5 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0
R6 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0
R7 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0
R8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
R9 0 0 0 OSC_2X 0 1 1 0 0 0 0 0 0 1 0 0
R10 0 0 0 1 MULT 1 0 1 1 0 0 0
R11 0 0 0 0 PLL_R 1 0 0 0
R12 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1
R13 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R14 0 0 0 1 0 0 1 1 1 CPG 0 0 0 0
R15 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1
R16 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
R17 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0
R18 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0
R19 0 0 1 0 0 1 1 1 1 0 1 1 0 1 1 1
R20 1 1 1 1 1 0 0 0 0 1 0 0 1 0 0 0
R21 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
R22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R23 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0
R24 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 0
R25 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0
R26 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0
R27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
R28 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0
R29 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0
R30 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0
R31 0 1 0 0 0 0 1 1 1 1 1 0 1 1 0 0
R32 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1
R33 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1
R34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R35 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
R36 PLL_N
R37 1 0 PFD_DLY_SEL 0 0 0 0 0 1 0 0
R38 PLL_DEN[31:16]
R39 PLL_DEN[15:0]
R40 MASH_SEED[31:16]
R41 MASH_SEED[15:0]
R42 PLL_NUM[31:16]
R43 PLL_NUM[15:0]
R44 0 0 0 1 1 1 1 1 LO_OUT_PD 0 MASH_RESET_N 0 0 MASH_ORDER
R45 1 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1
R46 0 0 0 0 0 1 1 1 1 1 1 1 1 1 LO_OUT_MUX
R47 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
R48 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
R49 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0
R50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R51 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
R52 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
R53 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R56 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R57 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R58 SYNC_PIN_IGNORE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LD_TYPE
R60 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0
R61 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
R62 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
R63 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R64 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0
R65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R66 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0
R67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R68 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0
R69 MASH_RST_COUNT[31:16]
R70 MASH_RST_COUNT[15:0]
R71 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1
R72 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R73 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
R74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R75 0 0 0 0 1 CHDIV 0 0 0 0 0 0
R76 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
R77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R78 0 0 0 0 0 0 VCO_CALSTART_CLOSE 0 0 1 1 0 0 1 0 0
R79 0 LO_PATH_EN 0 0 0 0 0 IFA_PULLUP_EN 0 0 0 LNA_PD SIGPATH_RST SIGCHAIN_PD
R80 0 0 0 0 SYNC_PHASE_MIXLO SYNC_DRV2_EN SYNC_DRV1_EN 0 0 0 LO_MUX
R81 0 0 0 0 LO_POLY_MODE1 EXTLO_CLK_DIV_EN LO_DRVR_MODE 0 EXTLO_CLK_DRV_EN SM_CLK_SEL
R82 0 0 0 0 1 0 1 0 0 0 EXTLO_DIV
R83 IFA_PULLUP VCM_CONFIG 0 0 0 1 0 0 0 0 1
R84 DCOC_CLK_DIV 0 0 0 0 EN_DCOC_QCH_LUT EN_DCOC_ICH_LUT
R85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R86 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R88 rb_DCOC_CAL 0 0 0 0 0 0 0 0 0 0 0 0 1 1
R89 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R91 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R92 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R93 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R94 IMRR_GCAL_QCH IMRR_GCAL_ICH
R95 IMRR_PHCAL_POL IMRR_PHCAL 0 0 0 0 0 0 0 0 0
R96 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0
R97 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R98 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
R101 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
R102 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R103 0 0 LO_POLY_MODE2 0 0 0 0 0 0 0 0 0 0
R104 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0
R105 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
R106 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R109 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R110 0 0 0 0 0 rb_LD_VTUNE 0 rb_VCO_SEL 0 0 0 0 0
R111 0 0 0 0 0 0 0 0 rb_VCO_CAPCTRL
R112 0 0 0 0 0 0 0 rb_VCO_DACISET
R113 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R114 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R115 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
R116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R117 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
R118 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R119 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
R120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R121 0 0 0 0 0 0 0 0 0 BIAS_LNA_CUR_CONFIG 0 0 0 0 0
R122 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R123 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTLO_INT_MATCH_RES
R124 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R125 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R126 IMRR_PHCAL_EXTEND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R127 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 7 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 7 should be considered as reserved locations and the register contents should not be modified.

Table 7. Device Registers

Address Acronym Register Name Section
0x0 R0 Go
0x1 R1 Go
0x2 R2 Go
0x9 R9 Go
0xA R10 Go
0xB R11 Go
0xE R14 Go
0x24 R36 Go
0x25 R37 Go
0x26 R38 Go
0x27 R39 Go
0x28 R40 Go
0x29 R41 Go
0x2A R42 Go
0x2B R43 Go
0x2C R44 Go
0x2E R46 Go
0x3A R58 Go
0x3B R59 Go
0x45 R69 Go
0x46 R70 Go
0x4B R75 Go
0x4E R78 Go
0x4F R79 Go
0x50 R80 Go
0x51 R81 Go
0x52 R82 Go
0x53 R83 Go
0x54 R84 Go
0x58 R88 Go
0x5E R94 Go
0x5F R95 Go
0x67 R103 Go
0x6E R110 Go
0x6F R111 Go
0x70 R112 Go
0x79 R121 Go
0x7B R123 Go
0x7E R126 Go

Complex bit access types are encoded to fit into small table cells. Table 8 shows the codes that are used for access types in this section.

Table 8. Device Access Type Codes

Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value