ZHCSCK8H May   2014  – April 2025 LP8860-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
    1.     Pin Functions
  7. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Current Sinks Electrical Characteristics
    7. 5.7  Boost Converter Characteristics
    8. 5.8  Logic Interface Characteristics
    9. 5.9  VIN Undervoltage Protection (VIN_UVLO)
    10. 5.10 VDD Undervoltage Protection (VDD_UVLO)
    11. 5.11 VIN Overvoltage Protection (VIN_OVP)
    12. 5.12 VIN Overcurrent Protection (VIN_OCP)
    13. 5.13 Power-Line FET Control Electrical Characteristics
    14. 5.14 External Temp Sensor Control Electrical Characteristics
    15. 5.15 I2C Serial Bus Timing Parameters (SDA, SCLK)
    16. 5.16 SPI Timing Requirements
    17. 5.17 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Boost Controller
      2. 6.1.2 LED Output Configurations
      3. 6.1.3 Display Mode
      4. 6.1.4 Cluster Mode
      5. 6.1.5 Hybrid Dimming
      6. 6.1.6 Charge Pump and Square Waveform (SQW) Output
      7. 6.1.7 Power-Line FET
      8. 6.1.8 Protection Features
      9. 6.1.9 Advanced Thermal Protection Features
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Clock Generation
        1. 6.3.1.1 LED PWM Clock Generation With VSYNC
        2. 6.3.1.2 LED PWM Frequency and Resolution
      2. 6.3.2 Brightness Control (Display Mode)
        1. 6.3.2.1 PWM Input Duty Cycle Based Control
        2. 6.3.2.2 Brightness Register Control
        3. 6.3.2.3 PWM Input Duty × Brightness Register
        4. 6.3.2.4 PWM-Input Direct Control
        5. 6.3.2.5 Brightness Slope
        6. 6.3.2.6 LED Dimming Methods
        7. 6.3.2.7 PWM Calculation Data Flow for Display Mode
      3. 6.3.3 LED Output Modes and Phase Shift PWM (PSPWM) Scheme
      4. 6.3.4 LED Current Setting
      5. 6.3.5 Cluster Mode
      6. 6.3.6 Boost Controller
      7. 6.3.7 Charge Pump
      8. 6.3.8 Powerline Control FET
      9. 6.3.9 Protection and Fault Detection Modes
        1. 6.3.9.1 LED Fault Comparators and Adaptive Boost Control
        2. 6.3.9.2 LED Current Dimming With Internal Temperature Sensor
        3. 6.3.9.3 LED Current Limitation With External NTC Sensor
        4. 6.3.9.4 LED Current Dimming With External NTC Sensor
        5. 6.3.9.5 Protection Feature and Fault Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby Mode
      2. 6.4.2 Active Mode
      3. 6.4.3 Fault Recovery State
      4. 6.4.4 Start-Up and Shutdown Sequences
    5. 6.5 Programming
      1. 6.5.1 EEPROM
      2. 6.5.2 Serial Interface
        1. 6.5.2.1 SPI Interface
        2. 6.5.2.2 I2C Serial Bus Interface
          1. 6.5.2.2.1 Interface Bus Overview
          2. 6.5.2.2.2 Data Transactions
          3. 6.5.2.2.3 Acknowledge Cycle
          4. 6.5.2.2.4 Acknowledge After Every Byte Rule
          5. 6.5.2.2.5 Addressing Transfer Formats
          6. 6.5.2.2.6 Control Register Write Cycle
          7. 6.5.2.2.7 Control Register Read Cycle
    6. 6.6 Register Maps
      1. 6.6.1 Register Bit Explanations
        1. 6.6.1.1  Display/Cluster1 Brightness Control MSB
        2. 6.6.1.2  Display/Cluster1 Brightness Control LSB
        3. 6.6.1.3  Display/Cluster1 Output Current MSB
        4. 6.6.1.4  Display/Cluster1 Output Current LSB
        5. 6.6.1.5  Cluster2 Brightness Control MSB
        6. 6.6.1.6  Cluster2 Brightness Control LSB
        7. 6.6.1.7  Cluster2 Output Current
        8. 6.6.1.8  Cluster3 Brightness Control MSB
        9. 6.6.1.9  Cluster3 Brightness Control LSB
        10. 6.6.1.10 Cluster3 Output Current
        11. 6.6.1.11 Cluster4 Brightness Control MSB
        12. 6.6.1.12 Cluster4 Brightness Control LSB
        13. 6.6.1.13 Cluster4 Output Current
        14. 6.6.1.14 Configuration
        15. 6.6.1.15 Status
        16. 6.6.1.16 Fault
        17. 6.6.1.17 LED Fault
        18. 6.6.1.18 Fault Clear
        19. 6.6.1.19 Identification
        20. 6.6.1.20 Temp MSB
        21. 6.6.1.21 Temp LSB
        22. 6.6.1.22 Display LED Current MSB
        23. 6.6.1.23 Display LED Current LSB
        24. 6.6.1.24 Display LED PWM MSB
        25. 6.6.1.25 Display LED PWM LSB
        26. 6.6.1.26 EEPROM Control
        27. 6.6.1.27 EEPROM Unlock Code
      2. 6.6.2 EEPROM Bit Explanations
        1. 6.6.2.1  EEPROM Register 0
        2. 6.6.2.2  EEPROM Register 1
        3. 6.6.2.3  EEPROM Register 2
        4. 6.6.2.4  EEPROM Register 3
        5. 6.6.2.5  EEPROM Register 4
        6. 6.6.2.6  EEPROM Register 5
        7. 6.6.2.7  EEPROM Register 6
        8. 6.6.2.8  EEPROM Register 7
        9. 6.6.2.9  EEPROM Register 8
        10. 6.6.2.10 EEPROM Register 9
        11. 6.6.2.11 EEPROM Register 10
        12. 6.6.2.12 EEPROM Register 11
        13. 6.6.2.13 EEPROM Register 12
        14. 6.6.2.14 EEPROM Register 13
        15. 6.6.2.15 EEPROM Register 14
        16. 6.6.2.16 EEPROM Register 15
        17. 6.6.2.17 EEPROM Register 16
        18. 6.6.2.18 EEPROM Register 17
        19. 6.6.2.19 EEPROM Register 18
        20. 6.6.2.20 EEPROM Register 19
        21. 6.6.2.21 EEPROM Register 20
        22. 6.6.2.22 EEPROM Register 21
        23. 6.6.2.23 EEPROM Register 22
        24. 6.6.2.24 EEPROM Register 23
        25. 6.6.2.25 EEPROM Register 24
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Application for Display Backlight
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Inductor Selection
          2. 7.2.1.2.2  Output Capacitor Selection
          3. 7.2.1.2.3  Input Capacitor Selection
          4. 7.2.1.2.4  Charge Pump Output Capacitor
          5. 7.2.1.2.5  Charge Pump Flying Capacitor
          6. 7.2.1.2.6  Diode
          7. 7.2.1.2.7  Boost Converter Transistor
          8. 7.2.1.2.8  Boost Sense Resistor
          9. 7.2.1.2.9  Power Line Transistor
          10. 7.2.1.2.10 Input Current Sense Resistor
          11. 7.2.1.2.11 Filter Component Values
            1. 7.2.1.2.11.1 Critical Components for Design
        3. 7.2.1.3 Application Performance Plots
      2. 7.2.2 Low VDD Voltage and Combined Output Mode Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Performance Plots
      3. 7.2.3 High Output Voltage Application
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Performance Plots
      4. 7.2.4 High Output Current Application
        1. 7.2.4.1 Design Requirements
        2. 7.2.4.2 Detailed Design Procedure
        3. 7.2.4.3 Application Performance Plots
      5. 7.2.5 Three-Channel Configuration Without Serial Interface
        1. 7.2.5.1 Design Requirements
        2. 7.2.5.2 Detailed Design Procedure
        3. 7.2.5.3 Application Performance Plots
      6. 7.2.6 Solution With Minimum External Components
        1. 7.2.6.1 Design Requirements
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

6.3.1.2 LED PWM Frequency and Resolution

LED output PWM frequency is selected with <PWM_FREQ[3:0]> EEPROM register when using a 5MHz internal oscillator for generating PWM output. <LED_STRING_CONF[2:0]> bits define phase shift between LED outputs as described later. <PWM_RESOLUTION[1:0]> EEPROM bits select the PLL output frequency and hence the LED PWM resolution. PWM frequencies with <EN_SYNC> = 0 are listed in Table 6-1.

Note:

If the VSYNC signal is used for generating PWM output frequency, it affects all clock frequencies, as well as the LED PWM output frequency. The Section 6.6.2 section explains how all the dividers affect the output clocks.

LP8860-Q1 PWM Clocking With Internal OscillatorFigure 6-2 PWM Clocking With Internal Oscillator
LP8860-Q1 PWM Clocking With PLL, Internal Oscillator as ReferenceFigure 6-3 PWM Clocking With PLL, Internal Oscillator as Reference
Table 6-1 Output PWM Frequency and Resolution With Internal Oscillator
00
OSC = 5MHz		 01
OSC = 10MHz		 10
OSC = 20MHz		 11
OSC = 40MHz
PWM_FREQ[3:0] PWM_RESOLUTION[1:0]
PWM FREQUENCY (Hz)		 RESOLUTION (bit)
1111 39063 7 8 9 10
1110 34180 7 8 9 10
1101 30518 7 8 9 10
1100 29297 7 8 9 10
1011 28076 7 8 9 10
1010 26855 7 8 9 10
1001 25635 7 8 9 10
1000 24412 7 8 9 10
0111 23192 7 8 9 10
0110 21973 7 8 9 10
0101 20752 7 8 9 10
0100 19531 8 9 10 11
0011 17090 8 9 10 11
0010 13428 8 9 10 11
0001 9766 9 10 11 12
0000 4883 10 11 12 13
LP8860-Q1 PWM Synchronization With External VSYNC Input Figure 6-4 PWM Synchronization With External VSYNC Input

PWM clock frequencies with different <SEL_DIVIDER>, <EN_PLL>, and <EN_SYNC> combinations are listed in Table 6-2.

Table 6-2 PLL Clock and LED PWM Frequency
PWM_SYNC SEL_DIVIDER EN_PLL EN_SYNC PLL CLOCK PWM FREQUENCY
0 X 0 0 5MHz See Table 6-1
0 1 1 0 5, 10, 20, 40MHz See Table 6-1
0 0 1 1 SYNC × R_SEL[1:0] × SLOW_PLL_DIV[12:0]/
SYNC_PRE_DIV[3:0]		 PLL clock / GEN_DIV
1 0 1 1 SYNC × GEN_DIV × SLOW_PLL_DIV[12:0]/
SYNC_PRE_DIV[3:0]		 PLL clock / GEN_DIV

GEN_DIV coefficients and resolution (bit) are listed on Table 6-3.

Table 6-3 GEN_DIV Coefficients and Resolution
PWM_RESOLUTION[1:0]
00 01 10 11
PWM_
FREQ[3:0]		 STEP GEN_DIV RES
(bits)		 STEP GEN_DIV RES
(bits)		 STEP GEN_DIV RES
(bits)		 STEP GEN_DIV RES
(bits)
0000 64 1024.00 10 32 2048.00 11 16 4096.00 12 8 8192.00 13
0001 128 512.00 9 64 1024.00 10 32 2048.00 11 16 4096.00 12
0010 176 372.36 8 88 744.73 9 44 1489.45 10 22 2978.91 11
0011 224 292.57 8 112 585.14 9 56 1170.29 10 28 2340.57 11
0100 256 256.00 8 128 512.00 9 64 1024.00 10 32 2048.00 11
0101 272 240.94 7 136 481.88 8 68 963.76 9 34 1927.53 10
0110 288 227.56 7 144 455.11 8 72 910.22 9 36 1820.44 10
0111 304 215.58 7 152 431.16 8 76 862.32 9 38 1724.63 10
1000 320 204.80 7 160 409.60 8 80 819.20 9 40 1638.40 10
1001 336 195.05 7 168 390.10 8 84 780.19 9 42 1560.38 10
1010 352 186.18 7 176 372.36 8 88 744.73 9 44 1489.45 10
1011 368 178.09 7 184 356.17 8 92 712.35 9 46 1424.70 10
1100 384 170.67 7 192 341.33 8 96 682.67 9 48 1365.33 10
1101 400 163.84 7 200 327.68 8 100 655.36 9 50 1310.72 10
1110 448 146.29 7 224 292.57 8 112 585.14 9 56 1170.29 10
1111 512 128.00 7 256 256.00 8 128 512.00 9 64 1024.00 10

Dithering allows increased resolution and smaller average steps size. Dithering can be programmed with EEPROM bits <DITHER[2:0]> 0 to 4 bits. Figure 6-5 shows 1-bit dithering. For 3-bit dithering, every 8th pulse is made 1 LSB longer to increase the average value by 1/8th. Dither is available in steady state condition when <EN_STEADY_DITHER> is high, otherwise during slope only.

LP8860-Q1 Example of the Dithering, 1-Bit Dither, 10-Bit Resolution Figure 6-5 Example of the Dithering, 1-Bit Dither, 10-Bit Resolution