ZHCSCK8H May 2014 – April 2025 LP8860-Q1
PRODUCTION DATA
Address 0x65
| EEPROM REGISTER 5 | |||||||
|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| I_SLOPE[2:0] | PWM_RESOLUTION[1:0] | DITHER[2:0] | |||||
| Name | Bit | Access | Description |
|---|---|---|---|
| I_SLOPE[2:0] | 7:5 | R/W | Slope gain adjusts the current slope for Hybrid PWM and Current dimming mode 000 = 1.000 001 = 1.023 010 = 1.047 011 = 1.070 100 = 1.094 101 = 1.117 110 = 1.141 111 = 1.164 |
| PWM_RESOLUTION[1:0] | 4:3 | R/W | For PWM clocking with internal oscillator (VSYNC is not used) these bits control the PLL multiplier and hence the PWM output resolution 00 = 5-MHz clock used for generating PWM 01 = 10-MHz clock used for generating PWM 10 = 20-MHz clock used for generating PWM 11 = 40-MHz clock used for generating PWM |
| DITHER[2:0] | 2:0 | R/W | Dither function controls 000 = Dither function disabled 001 = 1-bit dither 010 = 2-bit dither 011 = 3-bit dither 1XX = 4-bit dither |