以下 I²C 脚本在器件复位后将四个器件设置为共享 TDM 模式：

# Key: w NN YY ZZ ==> write to I2C address 0xNN, to register 0xYY, data 0xZZ
#               # ==> comment delimiter
#
# I2C programming script for four devices sharing a TDM bus
#  U4(SDOUT) -> U3 (SDOUT) -> U2 (SDOUT) -> U1 (SDOUT) -> Host Processor
#
#########################################################################
# Power-up Sequence:
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#########################################################################
# Wake-up devices
w 98 02 81  # Wake-up Device U1
w 9A 02 81  # Wake-up Device U2
w 9C 02 81  # Wake-up Device U3
w 9E 02 81  # Wake-up Device U4
d 10        # 10 ms delay
# Program Device A (U1), interfaces to host processor
w 98 00 00  # Set Device page register to Page 0 
w 98 07 31  # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity, 
            # default TX edge, Hi-Z for unused cycles
w 98 08 A0  # ASI transmit LSB for 1st half cycle, Hi-Z for second half cycle, 
            # bus keeper always enabled
w 98 0B 00  # ASI primary output (SDOUT) with CH1 assigned to slot 0
w 98 0C 01  # ASI primary output (SDOUT) with CH2 assigned to slot 1
w 98 0D 02  # ASI primary output (SDOUT) with CH3 assigned to slot 2
w 98 0E 03  # ASI primary output (SDOUT) with CH4 assigned to slot 3
w 98 73 F0  # Enable Ch1-4 of Device A
w 98 74 F0  # Enable Ch1-4 ASI output of Device A
# Program Device B (U2)
w 9A 00 00  # Set Device page register to Page 0 
w 9A 07 31  # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity, 
            # default TX edge, Hi-Z for unused cycles
w 9A 08 80  # ASI transmit LSB for 1st half cycle, Hi-Z for second half cycle, 
            # bus keeper disabled
w 9A 0B 04  # ASI primary output (SDOUT) with CH1 assigned to slot 4
w 9A 0C 05  # ASI primary output (SDOUT) with CH2 assigned to slot 5
w 9A 0D 06  # ASI primary output (SDOUT) with CH3 assigned to slot 6
w 9A 0E 07  # ASI primary output (SDOUT) with CH4 assigned to slot 7
w 9A 73 F0  # Enable Ch1-4 of Device B
w 9A 74 F0  # Enable Ch1-4 ASI output of Device B
# Program Device C (U3)
w 9C 00 00  # Set Device page register to Page 0 
w 9C 07 31  # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity, 
            # default TX edge, Hi-Z for unused cycles
w 9C 08 80  # ASI transmit LSB for 1st half cycle, Hi-Z for second half cycle, 
            # bus keeper disabled
w 9C 0B 08  # ASI primary output (SDOUT) with CH1 assigned to slot 8
w 9C 0C 09  # ASI primary output (SDOUT) with CH2 assigned to slot 9
w 9C 0D 0A  # ASI primary output (SDOUT) with CH3 assigned to slot 10
w 9C 0E 0B  # ASI primary output (SDOUT) with CH4 assigned to slot 11
w 9C 73 F0  # Enable Ch1-4 of Device C
w 9C 74 F0  # Enable Ch1-4 ASI output of Device C
# Program Device D (U4)
w 9E 00 00  # Set Device page register to Page 0 
w 9E 07 31  # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity, 
            # default TX edge, Hi-Z for unused cycles
w 9E 08 80  # ASI transmit LSB for 1st half cycle, Hi-Z for second half cycle, 
            # bus keeper disabled
w 9E 0B 0C  # ASI primary output (SDOUT) with CH1 assigned to slot 12
w 9E 0C 0D  # ASI primary output (SDOUT) with CH2 assigned to slot 13
w 9E 0D 0E  # ASI primary output (SDOUT) with CH3 assigned to slot 14
w 9E 0E 0F  # ASI primary output (SDOUT) with CH4 assigned to slot 15
w 9E 73 F0  # Enable Ch1-4 of Device D
w 9E 74 F0  # Enable Ch1-4 ASI output of Device D
# Power-up Devices A, B, C, & D
w 98 75 60  # Power up ADC and PLL of Device A
w 9A 75 60  # Power up ADC and PLL of Device B
w 9C 75 60  # Power up ADC and PLL of Device C
w 9E 75 60  # Power up ADC and PLL of Device D