SPRZ457J January   2021  – October 2025 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2287
      2.      i2330
      3.      i2351
      4.      i2424
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2103
      4.      i2184
      5.      i2189
      6.      i2236
      7.      i2185
      8.      i2196
      9.      i2207
      10.      i2208
      11.      i2228
      12.      i2232
      13.      i2244
      14.      i2245
      15.      i2091
      16.      i2235
      17.      i2303
      18.      i2317
      19.      i2134
      20.      i2257
      21.      i2277
      22.      i2285
      23.      i2310
      24.      i2311
      25.      i2313
      26.      i2328
      27.      i2241
      28.      i2279
      29.      i2307
      30.      i2320
      31.      i2329
      32.      i2331
      33.      i2243
      34.      i2249
      35.      i2256
      36.      i2274
      37.      i2278
      38.      i2306
      39.      i2363
      40.      i2312
      41.      i2371
      42.      i2366
      43.      i2138
      44.      i2253
      45.      i2259
      46.      i2283
      47.      i2305
      48.      i2326
      49.      i2368
      50.      i2383
      51.      i2401
      52.      i2409
      53.      i2291
      54.      i2413
      55.      i2414
      56.      i2415
      57.      i2417
      58.      i2418
      59.      i2419
      60.      i2420
      61.      i2422
      62.      i2423
      63.      i2431
      64.      i2433
      65.      i2434
      66.      i2435
      67.      i2436
      68.      i2160
      69.      i2482
  4.   Trademarks
  5.   Revision History

i2420

Boot: XSPI Boot time is not consistent in SFDP mode

Details:

When using xSPI boot with SFDP enabled (i.e. booting in DDR mode at 25Mhz) there is boot time variation across cold or warm boot. The issue is related to asynch bridge crossing in the OSPI subsystem, it is causing a race condition between:

  1. OSPI IP finishing its prefetch of data
  2. The next read transaction being submitted to the OSPI IP by the TI OSPI wrapper.
This introduces enough of a delay to cause the OSPI controller to de-assert chip select hence slowing down the overall transfer.

Workaround(s):

None