Revision(s) Affected:

AM65x SR 1.0

Details:

The Ring Accelerator (RINGACC) and the Unified DMA Controller (UDMA) each maintain their own state information about rings (queues). However, when a ring is reset in the RINGACC, the UDMA is unaware of this operation and its state information for that ring is not reset. As a result, the UDMA may believe a ring still has valid pending entries, while the RINGACC does not, and will potentially read invalid information from a recently reset and enabled ring.

Resetting a ring is a required operation (following DMA channel teardown operations and before re-enabling the DMA channels) when re-configuring an existing ring for another purpose (that is changing the ring mode, DMA channels, channel type, etc.).

Workaround(s):

The software workaround is to use the ring-mode doorbell functionality to cause the UDMA occupancy counter for a given ring to increment and wrap back to 0. Since a ring’s UDMA occupancy counter is 21-bits wide, and the highest doorbell ring count that can be written per register write is 127, the workaround requires a maximum of ((2**22) / 127) = 33,027 writes to the doorbell register. Note that a negative value cannot be used as the doorbell ring count value as the UDMA ignores negative values (a negative doorbell ring count value is seen by the UDMA as a ring pop count of abs(value) elements which it ignores in its ring state accounting).

To implement the software workaround, the following sequence should be used:

1. Read the ring occupancy (RINGACC_OCC_j [CNT]). If the ring occupancy is not 0, then steps 2-6 need to be executed to implement the workaround.
2. Reset the ring by writing any value in the RINGACC CFG registers (that is RINGACC_SIZE_j = RINGACC_SIZE_j).
3. Read the ring mode (RINGACC_SIZE_j [QMODE]) to determine the “adjusted ring occupancy count” used in step 5.
   1. If the ring is configured for exposed ring mode or messaging mode, the “adjusted ring occupancy count” is equal to the ring occupancy.
   2. If the ring is configured in credentials mode or queue manager (QM) mode, the “adjusted ring occupancy count” is equal to the ring occupancy divided by 2. This is required because when in credentials mode or QM mode, each ring write increases the ring occupancy by 2 elements (one entry for the credentials, one entry for the data). However, the UDMA-P’s local occupancy counter only records the number of writes, and the ring occupancy, therefore, needs to be divided by 2 to convert back to the number of doorbell rings needed.
4. Setup the ring in exposed ring/doorbell mode, if not already in this mode (RINGACC_SIZE_j [QMODE] = 0).
5. Ring the doorbell (2**22 – (adjusted ring occupancy count)) times. This will wrap the internal UDMA-P ring state occupancy counter (which is 21-bits wide) to 0. (If possible, ring the doorbell with the maximum count each iteration to minimize the total number of writes.
6. Restore the original ring mode (if not exposed ring mode).

This will ultimately reset the UDMA state information for a ring so that the RINGACC and UDMA are both in the same reset state for that ring. This workaround must be executed only when the DMA channels associated with the ring are disabled.